The 66AK2H14 datasheet SPRS866E Table 8-30 Device State Control Registers table shows that the DEVSPEED register is at address 0x02620C98:
Where the encoding of the DEVSPEED register is shown as:
With a 66AK2H14 silicon revision 2 device in a EVMK2H Rev 4 address 0x02620C98, which is the DEVSPEED according to the datasheet, reads as zero:
The value of zero at address 0x02620C98 decodes as a Device Speed grade of 800MHz for the DSP and 800MHz for the ARM which isn't a valid combination according to Figure 2-1 of the datasheet:
Note that the value of 0x00020008 at address 0x02620C90 decodes as a Device Speed grade of 1200MHz for the DSP and 1400MHz for the ARM, which is a valid combination.
Looking at the uboot source code for the Keystone architecture shows that for a CPU_66AK2Hx the read_efuse_bootrom() function in arch/arm/mach-keystone/clock.c reads from two different address depending upon the cpu_revision():
static inline u32 read_efuse_bootrom(void)
{
if (cpu_is_k2hk() && (cpu_revision() <= 1))
return __raw_readl(KS2_REV1_DEVSPEED);
else
return __raw_readl(KS2_EFUSE_BOOTROM);
}
int get_max_arm_speed(int *spds)
{
u32 armspeed = read_efuse_bootrom();
armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
DEVSPEED_ARMSPEED_SHIFT;
return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
}
int get_max_dev_speed(int *spds)
{
u32 devspeed = read_efuse_bootrom();
devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
DEVSPEED_DEVSPEED_SHIFT;
return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
}
Where KS2_REV1_DEVSPEED is address 0x02620c98 and KS2_EFUSE_BOOTROM is address 0x02620c90. i.e. the uboot source code shows for a Rev 1.x device the Device Speed is expected to be read from address 0x02620c98 and for a Rev 2 or above device the Device Speed is expected to be read from address 0x02620C90. The uboot cpu_revision() function returns the VARIANT field of the JTAG ID (JTAGID) Register.
Suggest that the 66AK2H14 datasheet SPRS866 is updated to note that for Silicon Revision 2 the DEVSPEED register is at address 0x02620c90, rather than address 0x02620c98 for Silicon Revisions 1.0 and 1.1.
Also, are there any other registers which different between Silicon Revision 1.0 / 1.1 and 2.0? The 66AK2H14 datasheet SPRS866E doesn't seem to contain any mention of Silicon Revision 2.0.
