C6746 McBSP RFULL error when used together with EMIFA

Yasuhiro Kaizu

Hello engineers,

I am writing my own driver software for my C6746 board.
My board uses the following peripherals of C6746.

- McBSP0 and McBSP1: Each connected to an A/D converter.
- EMIFA Asynchronous I/F: Connected to two asynchronous SRAMs (CS2 and CS3).

Both McBSP and EMIFA function well when used separately.
However, when I start the McBSPs and then write to the external SRAM continuously, the McBSPs fall into RFULL error shortly.

I'm using the McBSP in FIFO mode. The FIFO is not full, but it stops reading from the Data Receive Register (DRR).
EDMA is not used. McBSP interrupt is enabled in frame sync mode (RINTM = 2h).

The McBSPs are externally clocked from the I2S A/D converters.
The sampling rate (FSR frequency) is 40 kHz.

The SRAMs are both 16Mbit asynchronous SRAM with 16bit interface.
Reading from the SRAM does not disturb the McBSP FIFO.
I see the error only when making write accesses.

I'm wondering what the EMIFA has to do with the McBSP FIFO.
What should I investigate on this problem?

Thank you.

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

Actually RFULL=1 in the serial port control register (SPCR) indicates that the receiver has experienced overrun error condition and this conditions is set when the following are met:

• DRR (Receive Data register) has not been read since the last RBR-to-DRR transfer.

• RBR (Receive buffer register) is full and an RBR-to-DRR copy has not occurred.

• RSR (Receive shift register) is full and an RSR-to-RBR transfer has not occurred.

The above cause occur only if DRR has not been read by the CPU since the last RBR-to-DRR transfer (RRDY= 1), an RBR-to-DRR copy does not take place until RRDY = 0. This prevents an RSR-to-RBR copy. New data arriving on the DR pin is shifted into RSR, and the previous contents of RSR are lost. Because of this data loss of previous contents, RFULL=1 is set in SPCR and this triggers the overrun error condition.

Please refer Section 24.2.7.5.1 in the C6748 TRM as below for more details on RFULL error condition and how to clear the RFULL bit:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

Thanks & regards,

Sivaraj K

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0 Yasuhiro Kaizu over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 150 points

Hi Sivaraj,

Thanks for your reply.

I have read the C6746 TRM but unfortunately I couldn't find the answer in it.
I'm using McBSP Read FIFO (RFIFOCTL::RENA = 1). The TRM says,

> If the Read FIFO is enabled and the McBSP makes a receive DMA request,
> the RFIFO reads RNUMDMA 32-bit words from the McBSP,
> if and when the RFIFO has space for RNUMDMA words.

I'm sure RNUMDMA is 1 and there is enough space in the RFIFO.
Under this condition, is there any possibility of overrun (RFULL) error?
What prevents the RFIFO from reading from DRR?
And why does this error occur only while writing to the SRAM?

Regards,
Yasuhiro K

0 Sivaraj Kuppuraj over 9 years ago in reply to Yasuhiro Kaizu

TI__Mastermind 35645 points

Hi,

Thanks for your update.

Did RFULL=1 in the serial port control register (SPCR)? This is the only condition which the receiver would experience overrun error condition when above mentioned conditions are met?

Kindly validate RFULL instead of RNUMDMA in SPCR.