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AM335x UART misses one byte of data

user4543752
Prodigy 190 points
Other Parts Discussed in Thread: AM3352

Refer to SDK6.0
【problem description】
    Step1、Two A8 am3352 boards, Send a set of data(0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa),from MasterA UART1 to SlaveB UART5
    Step2、Operation Process: Board Power down ——————>Board Power Up——————>Send a set of data(0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa) from UART1 to UART5
    Step3、Repeat above Operation . In this process,we found the receive data is not correct .
            
        
        1)Step2 ,there is a certain probability , Occurrence of the following conditions：
        
        First group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x0]
            
        Second    group    
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x47]
            
        Third group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x6d]

        Fourth group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x70]

        Fifth group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x2d]    

        Sixth group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xce]  

         
        Seventh group
            UART1 Send     [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa]
            UART5 Recv     [0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x7]   



        Problem phenomenon :The set of data is missed the first data,thus tha last data make up by random data.

【Doubts】
    1、According to the catched waveform chart, Data and waveform consistency;
    2、It only occur condition：power down and up
Therefore suspect :before am335x uart's Tx FiFo active，Did not do empty FIFO action ?

Waiting online~

  • 0
    TI__Guru**** 393215 points
    Before you power cycle the board that is sending the UART data you must make sure that both the UART FIFO and the UART THR register are empty.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 190 points
    Hi,Biser:
    Thanks to your reply~
    where is in drivers/tty/serial/omap-serial.c, the serial_omap_startup has been clear fifo by serial_omap_clear_fifos before UART work.

    The flow path:

    ——————>serial_omap_startup
    /*
    * Clear the FIFO buffers and disable them.
    * (they will be reenabled in set_termios())
    */
    ————>serial_omap_clear_fifos

    In fact, the log shown below:

    Recv 10 data :0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, i32Rtn:10 u16MatchNum:10
    Recv 10 data :0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, i32Rtn:10 u16MatchNum:10
    Recv 10 data :0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, i32Rtn:10 u16MatchNum:10
    Recv 10 data :0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, i32Rtn:10 u16MatchNum:10
    Recv 10 data :0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, i32Rtn:10 u16MatchNum:10
    Recv 10 data :0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x0, i32Rtn:10 u16MatchNum:0
    Recv 10 data :0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x47, i32Rtn:10 u16MatchNum:0
    Recv 10 data :0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0x6d, i32Rtn:10 u16MatchNum:0

    Question:
    UART has cleared FiFo before serial_omap_startup, why still exists problem during power down and up ?

    Thus, how to find a appropriate solution or where to clear fifo ?
  • 0 in reply to user4543752
    TI__Guru**** 393215 points
    Clearing the FIFO is one thing. What I suppose is happening is that there is still data being shifted out from the THR register on the sending side when you shut down. The situation could be the similar on the receiving side. To summarize:

    On the transmit side you must ensure that both transmit fifo AND transmit hold register are empty before shutdown.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 190 points

    Hi,Biser:

    Thanks your opinion:

    We can ensure TX_FIFO and UART_THR clean with transmitting data and shutdown before.

    Still a doubt:

    As UART_RHR offset=0h same with UART_THR.

    When it tranmits over and switch to recive mode, is it influent for UART_RHR that we write UART_THR 0 value?

    References:  spruh73l.pdf

  • 0 in reply to user4543752
    TI__Guru**** 393215 points
    These are two separate registers sharing the same address. THR is a write-only register, RHR is a read-only register. In other words, when you write to address offset 0x000 data goes to THR, when you read from 0x000 data comes from RHR.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 190 points

    Hi,Biser:

        As your advise:
            To ensure transmit_chars right that we execute the following statement. As shown in the figure :
            
        The modified code succeed solving the transmit_chars problem during power up and down.

        With IIR_THRI flag setting， as shown below:

        
        As the datasheet description, is there no risk of modification ?
        
        
        As the datasheet description, is there no risk of modification in the transmit_chars ?

  • 0 in reply to user4543752
    TI__Guru**** 393215 points
    I don't understand your last question. If the problem is solved what is the issue?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 190 points

    In SDK7.0 ,the Uart WorkFlow：

       /*1、 Load Driver */

       ——————>serial_omap_probe

           /*2、Clear FIFO Before Startup Port */

           ————>serial_omap_startup        

               /*

                * Clear the FIFO buffers and disable them.

                * (they will be reenabled in set_termios())

                */

               serial_omap_clear_fifos(up);

               /*3、Setup Uart port */

               ————>serial_omap_set_termios

                   ————>UART - Already started working .

       /* 4、Close Uart */

       ——————>serial_omap_stop_tx

           ————>serial_omap_shutdown

               /* 5、Clear FIFO Before shutdown Port */

               serial_omap_clear_fifos(up)

    According to the above process，actually ,I don't know the reason  ,

    What causes the serial port's problem during power up and down?