AM437x GPIO write value operation not permitted.

Ash P

Other Parts Discussed in Thread: AM4372

Hi Forum,

I am currently trying to toggle a gpio pin from user space and I am facing the following issues.

below is my dts

    gpio2_pins: gpio2_pins {
        pinctrl-single,pins = <
            0x90 	(PIN_OUTPUT |MUX_MODE7) /* (A9) gpmc_advn_ale.gpmc_advn_ale */
        >;
    };

&gpio2 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio2_pins>; 
	status = "okay";
};

when i try to implement the following i am unable to see the pin toggling in my logic analyzer.

root@am437x-evm:~# echo "out" > /sys/class/gpio/gpio66/direction                
root@am437x-evm:~# echo 1 > /sys/class/gpio/gpio66/value                        
root@am437x-evm:~# echo 1 > /sys/class/gpio/gpio66/value                        
root@am437x-evm:~# echo 0 > /sys/class/gpio/gpio66/value                        
root@am437x-evm:~# echo 0 > /sys/class/gpio/gpio66/value                        
root@am437x-evm:~# echo 1 > /sys/class/gpio/gpio66/value

is this the right way to do a gpio access or am i missing some steps??

the pin i am trying to currently access is gpio2_2 so the physical pin is (2*32)+2=66. 

-parker

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

I will ask the software team to look at this.

0 Kemal R. Shakir over 10 years ago in reply to Biser Gatchev-XID

TI__Guru 55345 points

Hello Parker,

Please check the file cat /sys/kernel/debug/gpio and see the gpio range for every enabled gpio bank address. If you have disabled or unused gpio banks the numbering range will be changed and the following (2*32)+2=66 formula will not work.

Best regards,
Kemal

0 Ash P over 10 years ago in reply to Kemal R. Shakir

Expert 1570 points

hi kemal,

here is the output

root@am437x-evm:~#  cat /sys/kernel/debug/gpio                                  
GPIOs 0-31, platform/44e07000.gpio, gpio:                                       
 gpio-3   (matrix_kbd_row      ) in  lo IRQ                                     
 gpio-6   (cd                  ) in  lo IRQ                                     
                                                                                
GPIOs 32-63, platform/4804c000.gpio, gpio:                                      
 gpio-48  (kim                 ) out lo                                         
 gpio-52  (vmmcwl_fixed        ) out lo                                         
                                                                                
GPIOs 64-95, platform/481ae000.gpio, gpio:                                      
 gpio-83  (matrix_kbd_col      ) out hi                                         
 gpio-84  (matrix_kbd_col      ) out hi                                         
                                                                                
GPIOs 96-127, platform/48320000.gpio, gpio:                                     
 gpio-98  (matrix_kbd_row      ) in  lo IRQ                                     
 gpio-99  (matrix_kbd_row      ) in  hi IRQ                                     
                                                                                
GPIOs 128-159, platform/48322000.gpio, gpio:                                    
 gpio-135 (vtt_fixed           ) out hi                                         
                                                                                
GPIOs 160-191, platform/481ac000.gpio, gpio:                                    
                                                                                
GPIOs 510-511, platform/50000000.gpmc, omap-gpmc:

so how do i find out the actual pin number for my gpio2_2 in that case ??

0 Kemal R. Shakir over 10 years ago in reply to Ash P

TI__Guru 55345 points

Now you can check your am4372.dtsi or the TRM section 2 Memory Map 2.1.3 L4_PER Peripheral Memory Map for corresponding addresses. In your case gpio2 bank is this. Range 64-95 which seems correctly mapped an the (2*32)+2=66 should work in this case.

GPIOs 64-95, platform/481ae000.gpio, gpio:
gpio-83 (matrix_kbd_col ) out hi
gpio-84 (matrix_kbd_col ) out hi

0 Ash P over 10 years ago in reply to Kemal R. Shakir

Expert 1570 points

Hi Kemal,
when i try the following there is nothing happening on the gpio 66 line
root@am437x-evm:~# echo "66" > /sys/class/gpio/export
root@am437x-evm:~# echo "out" > /sys/class/gpio/gpio66/direction
root@am437x-evm:~# echo "1" > /sys/class/gpio/gpio66/value
root@am437x-evm:~# echo "66" > /sys/class/gpio/unexport
is this the correct way of toggling the pin or am i doing something wrong here ???

-Parker

0 Kemal R. Shakir over 10 years ago in reply to Ash P

TI__Guru 55345 points

Yes, this is the correct procedure for toggling a gpio trough sysfs.

Could you execute this command and post the feedback:

root@am437x-evm:~# grep 44e10890 /sys/kernel/debug/pinctrl/44e10800.pinmux/pingroups

0 Ash P over 10 years ago in reply to Kemal R. Shakir

Expert 1570 points

Hi Kemal,

root@am437x-evm:/bin# grep 44e10890 /sys/kernel/debug/pinctrl/44e10800.pinmux/pingroups
pin 36 (44e10890.0)

am437x-evm:/bin#  cat /sys/kernel/debug/pinctrl/44e10800.pinmux/pingroups | 
registered pin groups:
group: pinmux_wlan_pins_default
pin 20 (44e10850.0)
pin 23 (44e1085c.0)
pin 16 (44e10840.0)

group: lcd_pins
pin 142 (44e10a38.0)

group: pinmux_debugss_pins
pin 164 (44e10a90.0)
pin 165 (44e10a94.0)
pin 166 (44e10a98.0)
pin 167 (44e10a9c.0)
pin 168 (44e10aa0.0)
pin 169 (44e10aa4.0)
pin 170 (44e10aa8.0)

group: unused_pins
pin 21 (44e10854.0)
pin 22 (44e10858.0)
pin 24 (44e10860.0)
pin 25 (44e10864.0)
pin 26 (44e10868.0)
pin 27 (44e1086c.0)
pin 104 (44e109a0.0)
pin 143 (44e10a3c.0)
pin 145 (44e10a44.0)
pin 146 (44e10a48.0)
pin 147 (44e10a4c.0)
pin 152 (44e10a60.0)
pin 154 (44e10a68.0)
pin 156 (44e10a70.0)
pin 158 (44e10a78.0)
pin 159 (44e10a7c.0)
pin 178 (44e10ac8.0)
pin 181 (44e10ad4.0)
pin 182 (44e10ad8.0)
pin 183 (44e10adc.0)
pin 184 (44e10ae0.0)
pin 185 (44e10ae4.0)
pin 186 (44e10ae8.0)
pin 187 (44e10aec.0)
pin 188 (44e10af0.0)
pin 189 (44e10af4.0)
pin 190 (44e10af8.0)
pin 191 (44e10afc.0)
pin 192 (44e10b00.0)
pin 193 (44e10b04.0)
pin 194 (44e10b08.0)
pin 195 (44e10b0c.0)
pin 196 (44e10b10.0)
pin 197 (44e10b14.0)
pin 198 (44e10b18.0)
         
group: board_pins
pin 155 (44e10a6c.0)
         
group: pinmux_wlan_pins_sleep
pin 20 (44e10850.0)
pin 23 (44e1085c.0)
pin 16 (44e10840.0)
         
group: uart0_pins_default
pin 90 (44e10968.0)
pin 91 (44e1096c.0)
pin 92 (44e10970.0)
pin 93 (44e10974.0)
         
group: uart0_pins_sleep
pin 90 (44e10968.0)
pin 91 (44e1096c.0)
pin 92 (44e10970.0)
pin 93 (44e10974.0)
         
group: uart3_pins
pin 138 (44e10a28.0)
pin 139 (44e10a2c.0)
         
group: spi0_pins
pin 84 (44e10950.0)
pin 85 (44e10954.0)
pin 86 (44e10958.0)
pin 87 (44e1095c.0)
pin 88 (44e10960.0)
pin 157 (44e10a74.0)
pin 100 (44e10990.0)
         
group: spi1_pins
pin 66 (44e10908.0)
pin 67 (44e1090c.0)
pin 68 (44e10910.0)
pin 81 (44e10944.0)
pin 89 (44e10964.0)
pin 101 (44e10994.0)
pin 102 (44e10998.0)
         
group: spi2_pins
pin 148 (44e10a50.0)
pin 149 (44e10a54.0)
pin 150 (44e10a58.0)
pin 151 (44e10a5c.0)
pin 140 (44e10a30.0)
         
group: cpsw_default
pin 69 (44e10914.0)
pin 70 (44e10918.0)
pin 71 (44e1091c.0)
pin 72 (44e10920.0)
pin 73 (44e10924.0)
pin 74 (44e10928.0)
pin 75 (44e1092c.0)
pin 76 (44e10930.0)
pin 77 (44e10934.0)
pin 78 (44e10938.0)
pin 79 (44e1093c.0)
pin 80 (44e10940.0)
         
group: cpsw_sleep
pin 69 (44e10914.0)
pin 70 (44e10918.0)
pin 71 (44e1091c.0)
pin 72 (44e10920.0)
pin 73 (44e10924.0)
pin 74 (44e10928.0)
pin 75 (44e1092c.0)
pin 76 (44e10930.0)
pin 77 (44e10934.0)
pin 78 (44e10938.0)
pin 79 (44e1093c.0)
pin 80 (44e10940.0)
         
group: davinci_mdio_default
pin 82 (44e10948.0)
pin 83 (44e1094c.0)
         
group: davinci_mdio_sleep
pin 82 (44e10948.0)
pin 83 (44e1094c.0)
         
group: pinmux_mmc1_pins
pin 64 (44e10900.0)
pin 65 (44e10904.0)
pin 60 (44e108f0.0)
pin 61 (44e108f4.0)
pin 62 (44e108f8.0)
pin 63 (44e108fc.0)
pin 88 (44e10960.0)
         
group: pinmux_mmc1_sleep_pins
pin 64 (44e10900.0)
pin 65 (44e10904.0)
pin 60 (44e108f0.0)
pin 61 (44e108f4.0)
pin 62 (44e108f8.0)
pin 63 (44e108fc.0)
pin 88 (44e10960.0)
         
group: gpio2_pins
pin 36 (44e10890.0)
pin 38 (44e10898.0)
         
group: i2c0_pins
pin 98 (44e10988.0)
pin 99 (44e1098c.0)
         
group: dcan0_default_pins
pin 94 (44e10978.0)
pin 95 (44e1097c.0)
         
group: vpfe0_pins_default
pin 108 (44e109b0.0)
pin 109 (44e109b4.0)
pin 112 (44e109c0.0)
pin 113 (44e109c4.0)
pin 114 (44e109c8.0)
pin 130 (44e10a08.0)
pin 131 (44e10a0c.0)
pin 132 (44e10a10.0)
pin 133 (44e10a14.0)
pin 134 (44e10a18.0)
pin 135 (44e10a1c.0)
pin 136 (44e10a20.0)
pin 137 (44e10a24.0)
         
group: vpfe0_pins_sleep
pin 108 (44e109b0.0)
pin 109 (44e109b4.0)
pin 112 (44e109c0.0)
pin 113 (44e109c4.0)
pin 114 (44e109c8.0)
pin 130 (44e10a08.0)
pin 131 (44e10a0c.0)
pin 132 (44e10a10.0)
pin 133 (44e10a14.0)
pin 134 (44e10a18.0)
pin 135 (44e10a1c.0)
pin 136 (44e10a20.0)
pin 137 (44e10a24.0)
         
group: pixcir_ts_pins_default
pin 153 (44e10a64.0)
         
group: pixcir_ts_pins_sleep
pin 153 (44e10a64.0)
         
group: dcan1_default_pins
pin 96 (44e10980.0)
pin 97 (44e10984.0)
         
group: vpfe1_pins_default
pin 115 (44e109cc.0)
pin 116 (44e109d0.0)
pin 117 (44e109d4.0)
pin 118 (44e109d8.0)
pin 119 (44e109dc.0)
pin 122 (44e109e8.0)
pin 123 (44e109ec.0)
pin 124 (44e109f0.0)
pin 125 (44e109f4.0)
pin 126 (44e109f8.0)
pin 127 (44e109fc.0)
pin 128 (44e10a00.0)
pin 129 (44e10a04.0)
         
group: vpfe1_pins_sleep
pin 115 (44e109cc.0)
pin 116 (44e109d0.0)
pin 117 (44e109d4.0)
pin 118 (44e109d8.0)
pin 119 (44e109dc.0)
pin 122 (44e109e8.0)
pin 123 (44e109ec.0)
pin 124 (44e109f0.0)
pin 125 (44e109f4.0)
pin 126 (44e109f8.0)
pin 127 (44e109fc.0)
pin 128 (44e10a00.0)
pin 129 (44e10a04.0)
         
group: usb2_phy2_default
pin 177 (44e10ac4.0)
         
group: usb2_phy2_sleep
pin 177 (44e10ac4.0)
         
group: matrix_keypad_default
pin 105 (44e109a4.0)
pin 106 (44e109a8.0)
pin 107 (44e109ac.0)
         
group: matrix_keypad_sleep
pin 105 (44e109a4.0)
pin 106 (44e109a8.0)
pin 107 (44e109ac.0)

is the output

-Parker

0 Ash P over 10 years ago in reply to Kemal R. Shakir

Expert 1570 points

Hi Kemal,

I have grouped my gpio as following but still cannot see them toggle.

group: gpio1_pins_default                                                       
pin 10 (44e10828.0)                                                             
pin 11 (44e1082c.0)                                                             
pin 29 (44e10874.0)                                                             
                                                                                
group: gpio2_pins_default                                                       
pin 0 (44e10800.0)                                                              
pin 1 (44e10804.0)                                                              
pin 2 (44e10808.0)                                                              
pin 3 (44e1080c.0)                                                              
pin 4 (44e10810.0)                                                              
pin 5 (44e10814.0)                                                              
pin 6 (44e10818.0)                                                              
pin 7 (44e1081c.0)                                                              
pin 12 (44e10830.0)                                                             
pin 13 (44e10834.0)                                                             
pin 14 (44e10838.0)                                                             
pin 15 (44e1083c.0)                                                             
pin 30 (44e10878.0)                                                             
pin 31 (44e1087c.0)                                                             
                                                                                
group: gpio3_pins_default                                                       
pin 34 (44e10888.0)                                                             
pin 35 (44e1088c.0)                                                             
pin 36 (44e10890.0)                                                             
pin 37 (44e10894.0)                                                             
pin 38 (44e10898.0)                                                             
pin 39 (44e1089c.0)                                                             
                                                                                
group: gpio4_pins_default                                                       
pin 9 (44e10824.0)                                                              
pin 8 (44e10820.0)                                                              
pin 28 (44e10870.0)

defined them in the device tree as follows

gpio1_pins_default: gpio1_pins_default {
	pinctrl-single,pins = <
		0x28 ( PIN_INPUT | MUX_MODE7 ) /* (F11) gpmc_ad10.gpio0[26] */
		0x2c ( PIN_INPUT | MUX_MODE7 ) /* (D11) gpmc_ad11.gpio0[27] */
		0x74 ( PIN_INPUT | MUX_MODE7 ) /* (B3) gpmc_wpn.gpio0[31] csn_5*/
	>;
};

gpio2_pins_default: gpio2_pins_default {
	pinctrl-single,pins = <
		0x0 ( PIN_INPUT | MUX_MODE7 ) /* (B5) gpmc_ad0.gpio1[0] */
		0x4 ( PIN_INPUT | MUX_MODE7 ) /* (A5) gpmc_ad1.gpio1[1] */
		0x8 ( PIN_INPUT | MUX_MODE7 ) /* (B6) gpmc_ad2.gpio1[2] */
		0xc ( PIN_INPUT | MUX_MODE7 ) /* (A6) gpmc_ad3.gpio1[3] */
		0x10 ( PIN_INPUT | MUX_MODE7 ) /* (B7) gpmc_ad4.gpio1[4] */
		0x14 ( PIN_INPUT | MUX_MODE7 ) /* (A7) gpmc_ad5.gpio1[5] */
		0x18 ( PIN_INPUT | MUX_MODE7 ) /* (C8) gpmc_ad6.gpio1[6] */
		0x1c ( PIN_INPUT | MUX_MODE7 ) /* (B8) gpmc_ad7.gpio1[7] */
		0x30 ( PIN_INPUT | MUX_MODE7 ) /* (E11) gpmc_ad12.gpio1[12] */
		0x34 ( PIN_INPUT | MUX_MODE7 ) /* (C11) gpmc_ad13.gpio1[13] */
		0x38 ( PIN_INPUT | MUX_MODE7 ) /* (B11) gpmc_ad14.gpio1[14] */
		0x3c ( PIN_INPUT | MUX_MODE7 ) /* (A11) gpmc_ad15.gpio1[15] */
		0x78 ( PIN_INPUT | MUX_MODE7 ) /* (A3) gpmc_be1n.gpio1[28]  csn_6*/
		0x7c ( PIN_INPUT | MUX_MODE7 ) /* (A8) gpmc_csn0.gpio1[29] */
	>;
};
gpio3_pins_default: gpio3_pins_default {
	pinctrl-single,pins = <
		0x88 ( PIN_INPUT | MUX_MODE7 ) /* (B12) gpmc_csn3.gpio2[0] */
		0x8c ( PIN_INPUT | MUX_MODE7 ) /* (A12) gpmc_clk.gpio2[1] */
		0x90 ( PIN_INPUT | MUX_MODE7 ) /* (A9) gpmc_advn_ale.gpio2[2] */
		0x94 ( PIN_INPUT | MUX_MODE7 ) /* (E10) gpmc_oen_ren.gpio2[3] */
		0x98 ( PIN_INPUT | MUX_MODE7 ) /* (D10) gpmc_wen.gpio2[4] */
		0x9c ( PIN_INPUT | MUX_MODE7 ) /* (C10) gpmc_be0n_cle.gpio2[5] */
	>;
};
gpio4_pins_default: gpio4_pins_default {
	pinctrl-single,pins = <
		0x24 ( PIN_INPUT | MUX_MODE9 ) /* (A10) gpmc_ad9.gpio5[25] */
		0x20 ( PIN_INPUT | MUX_MODE9 ) /* (B10) gpmc_ad8.gpio5[26] */
		0x70 ( PIN_INPUT | MUX_MODE9 ) /* (A2) gpmc_wait0.gpio5[30] */
	>;
};
&gpio0 {
	pinctrl-names = "default";
    	pinctrl-0 = <&gpio1_pins_default>; 
	status = "okay";
};

&gpio1 {
	pinctrl-names = "default";
    	pinctrl-0 = <&gpio2_pins_default>; 
	status = "okay";
};

&gpio2 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&gpio3_pins_default>; 
	status = "okay";
};

&gpio3 {
	pinctrl-names = "default";
    	pinctrl-0 = <&gpio4_pins_default>; 
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
	ti,no-reset-on-init;
};

my c program access is as follows

gpio_export(68);
gpio_set_dir(68, OUTPUT_PIN);
for(i=0;i<100;i++){
gpio_set_value(68, HIGH);
sleep(1);
gpio_set_value(68, LOW);
printf("toggle pin 68 done %d times\n",i);
}
gpio_unexport(68);
printf("toggle 68 done\n");

I am trying to access gpio2_2 I have also tried the user space as mentioned in the above steps without any success. any suggestions and help would be appreciated.

-Parker

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AM437x GPIO write value operation not permitted.