Ethernet Phy's compatible with AM1705

Hello Titus,

Thank you for your help. This is my first ARM design and I have just been gathering info on how to design the interfaces, ethernet among them.

As I wrote in the first message, I thought that RMII wasn't compatible with this processor because of the note:

that is shown in the features for the latest PSP for the AM1705 processor at:

http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.20.00.14_Device_Driver_Features_and_Performance_Guide#Ethernet_Driver

Please correct me if I'm wrong, but it seems that all the problems related to ethernet interface with these processors is because of the reference clock signal. If the clock is supplied by the AM1705 problems could arise due to the fact that the generated 50 MHz clock is not compliant with the RMII specification, which requires a max freq deviation of +/- 50ppm. This is also true when the clock is generated from the PHY chip.

This is suggested in the AM1705 literature and in PHY IC's literature as well:

In page 104 of the Tech Reference Manual SPRUH93B for the AM1705 processor there is a note warning this:

If we take the for example the Microchip LAN8720a, its datasheet also shows a note describing that if the clock generated from this PHY there could be potential problems as well:

So in conclusion it seems, that the best alternative (that is, to avoid problems) is to use an external clock generator with the required +/- 50 ppm stability.

I will really appreciate your opinion about my conclusion.

Best regards,

Patricio Cohen