Can't enable USB1_DRVVBUS on AM572x IDK

MilesWang

Other Parts Discussed in Thread: TPS2065

Dear sir,

We met problem when developing usb3.0 of vxworks based on am572x-IDK, the USB1_DRVVBUS cannot be enabled. CTRL_CORE_PAD_USB1_DRVVBUS is set to 0xC0000, and the PP bit of USB_PORTSCx is '1'. Is there any other register to control USB1_DRVVBUS?

Thanks,

Miles

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

I will ask the USB experts to comment.

0 MilesWang over 9 years ago in reply to Biser Gatchev-XID

Prodigy 60 points

Hi,

By the way there is a clock (USB1_FCLK) "USB2PHY1_UTMI_CLK" at the Table 24-566 "Clocks and Resets", in section 24.7.3 of AM572x Technical Reference Manual. I don't find its introduction. It should be the 60-MHz UTMI clock from PHY. How to output the 60MHz clock from USB2PHY1?

Thanks,

Miles

0 lding over 9 years ago in reply to MilesWang

TI__Guru* 95265 points

Miles,

Looks you want to enable the USB1 as host or DRD mode, which sets DRVVBUS to high and enables TPS2065 to output 5.0 volt to a USB device.

I also got feedback that you refer to TI u-boot code which worked fine, then you try to adapt to your VxWorks development. I looked at TI RTOS example for AM572x IDK EVM in either host mode or device mode (which worked), the CTRL_CORE_PAD_USB1_DRVVBUS (0x4a00_1680) is 0x0000_0000 which is set by pinmux. You mentioned CTRL_CORE_PAD_USB1_DRVVBUS is set to 0xC0000, that is different from my working case.

What is the USB_PORTSCx? I didn't find simliar name in the TRM? Can you explain?

Regards, Eric

0 MilesWang over 9 years ago in reply to lding

Prodigy 60 points

Eric,

CTRL_CORE_PAD_USB1_DRVVBUS should be 0x4a00_3680, not 0x4a00_1680. Please confirm it.

We got the value 0x000C_0000 from u-boot (u-boot works well). We also tried 0x0000_0000 in CTRL_CORE_PAD_USB1_DRVVBUS. The result failed too.

USB_PORTSCx is 0x280.

About USB2PHY1_UTMI_CLK, please see page 5994,Table 24-566 "Clocks and Resets" in TRM.

Thanks,

Miles

0 lding over 9 years ago in reply to MilesWang

TI__Guru* 95265 points

1680 is typo, should be 3680.

The setting of enabling DRVVBUS is done in below function in our RTOS code:

void USBOTGSS_WRAPPER_ForceVbus(uint32_t portNumber, uint32_t isDeviceMode)
{
uint32_t reg;

reg = HW_RD_REG32(USB_DWC3_WRAPPER_BASE_ADDR(portNumber) +
USB_WRAPPER_UTMI_OTG_STATUS);

if (isDeviceMode)
{
reg |= (1<<31); // SW_MODE
reg |= (1<<9); // Powerpresent??? (do we need this for device mode?)
reg |= (1<<4); // ID floating
reg |= (1<<2); // SESSVALID, VBUS above sessionvalid threshold???

reg |= (1<<3); // SESSEND = 0
reg |= (1<<1); // VBUS_VALID = 1
}
else
{
reg |= (1<<31); // SW_MODE
reg |= (1<<9); // Powerpresent
reg &= ~(1<<4); // ID = 0;
reg |= (1<<2); // SESSVALID, VBUS above sessionvalid threshold???

reg &= ~(1<<3); // SESSEND = 0
reg &= ~(1<<1); // VBUS_VALID = 0
reg |= (1<<3); // SESSEND = 0 //????????
}

HW_WR_REG32(USB_DWC3_WRAPPER_BASE_ADDR(portNumber) +
USB_WRAPPER_UTMI_OTG_STATUS, reg);
}

#define USB0_DWC_WRAPPER_BASE_ADDR (0x48880000)
#define USB1_DWC_WRAPPER_BASE_ADDR (0x488C0000)
#define USB_WRAPPER_UTMI_OTG_STATUS 0x0084

For host mode, isDeviceMode = 0. The u-boot code should be similar, can you check if you have above?

USB_PORTSCx is 0x280.====> This is mapped to:
#define DWC_USB_PORTSC1 (0x420u)
#define DWC_USB_PORTSC2 (0x430u)
#define USB_DWC_CORE_OFFSET (0x10000)

For working case where IDK572 EVM is USB host:
address 0x4888_0084: 0x8000_0018
address 0x4889_0420: 0xE03

Regards, Eric

0 MilesWang over 9 years ago in reply to lding

Prodigy 60 points

Hi Eric,

We're using USB1 (J23 on AM572x_IDK) in host mode. From upper USBOTGSS_WRAPPER_ForceVbus() API,USB_WRAPPER_UTMI_OTG_STATUS (0x4888_0084) should be 0x8000_020C, not 0x8000_0018. Please confirm it.

    reg |= (1<<31); // SW_MODE
    reg |= (1<<9); // Powerpresent
    reg &= ~(1<<4); // ID = 0;
    reg |= (1<<2); // SESSVALID, VBUS above sessionvalid threshold???
    reg &= ~(1<<3); // SESSEND = 0
    reg &= ~(1<<1); // VBUS_VALID = 0
    reg |= (1<<3); // SESSEND = 0 //????????

Both 0x8000_020C and 0x8000_0018 do not help.

We check uboot code and TRM. There are so many reset control on USB module as below (Not sure if it is complete):

1. USB_FLADJ (0x4888_0104): bit 31 (CORE_SW_RESET) - Active-high core software reset.
2. USB_DCTL (0x4889_C704): bit 30 (CSFTRST) - Core Soft Reset.
3. USB_GCTL (0x4889_C110): bit 11 (CORESOFTRESET) - Core Soft Reset.
4. USB_GUSB3PIPECTL (0x4889_C2C0): bit 31 (PHYSOFTRST) - PHY Soft Reset.
5. USB_GUSB2PHYCFG (0x4889_C200): bit 31 (PHYSOFTRST) - PHY Soft Reset.
6. USB_USBCMD (0x4889_0020): bit 1 (HCRST) - Host Controller Reset.

Can you show us the USB reset program flow?

Thanks,

Miles

0 lding over 9 years ago in reply to MilesWang

TI__Guru* 95265 points

Miles,

I looked our host test example, the call flow likes this:

usb_open_dwc====>setupDwcHostMsc====>usb_wrapper_setup_host_mode:

void usb_wrapper_setup_host_mode(uint32_t portNum)
{
uint32_t isDeviceMode = 0; // host mode.
USBOTGSS_WRAPPER_ForceVbus(portNum, isDeviceMode);

usb3_phy_reset(portNum);
}

I attached the driver code for your reference, including how we reset the PHY 5700.usb.zip

. I looked at the 0x4888_0084, it is 0x8000_0018.

Regards, Eric

0 MilesWang over 9 years ago in reply to lding

Prodigy 60 points

Eric,

The reset default value of 0x4888_0084 is 0x8000_0018. The result seem inconsistent to your code.

I checked your code included in "5700.usb.zip". Is it workable code? Please confirm usb3_phy_reset() API as below:

uint32_t dwc3BaseAddr;

dwc3BaseAddr = USB_DWC3_WRAPPER_BASE_ADDR(portNumber) + USB_DWC_CORE_OFFSET;

/* * PHYs Reset */

/* USB 2 PHY Reset */

HW_WR_FIELD32(dwc3BaseAddr, DWC_USB_GUSB2PHYCFG_PHYSOFTRST, DWC_USB_GUSB2PHYCFG_PHYSOFTRST_ACTIVE);

/* USB 3 PHY Reset */

HW_WR_FIELD32(dwc3BaseAddr, DWC_USB_GUSB3PIPECTL_PHYSOFTRST, DWC_USB_GUSB3PIPECTL_PHYSOFTRST_ACTIVE);

/* USB 3 PHY Reset */

HW_WR_FIELD32(dwc3BaseAddr, DWC_USB_GCTL_CORESOFTRESET, DWC_USB_GCTL_CORESOFTRESET_RESET);

Do you write the same register to reset USB2PHY and USB3PHY?

Thanks,

Miles

0 lding over 9 years ago in reply to MilesWang

TI__Guru* 95265 points

Miles,

The code I sent you is the working code we used in the latest Processor SDK 2.0.2 release: software-dl.ti.com/.../index_FDS.html , I zipped the USB driver folder to you. I used that code for AM572 IDK EVM testing in recent days, use the USB as host mode by plug in a USB key to see if I can emuerate it and do some simple command like: ls, dir, mkdir, mv, etc.... It always worked.

With do power cycle, the 0x4888_0084 is 0x0. As I step through the code function:
after USBOTGSS_WRAPPER_ForceVbus(), the register is still 0x0
after usb3_phy_reset(), the register is still 0x0
after USB_Host_Init(), the register is 0x8000_0018 and stay at this value

usb3_phy_reset code is in ub_wrapper.c starting from line 287:

void usb3_phy_reset(uint32_t portNumber)
{
uint32_t loop;
uint32_t dwc3BaseAddr;

dwc3BaseAddr = USB_DWC3_WRAPPER_BASE_ADDR(portNumber) + USB_DWC_CORE_OFFSET;

/*
* PHYs Reset
*/
/* USB 2 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GUSB2PHYCFG_PHYSOFTRST,
DWC_USB_GUSB2PHYCFG_PHYSOFTRST_ACTIVE);

/* USB 3 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GUSB3PIPECTL_PHYSOFTRST,
DWC_USB_GUSB3PIPECTL_PHYSOFTRST_ACTIVE);

/* USB 3 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GCTL_CORESOFTRESET,
DWC_USB_GCTL_CORESOFTRESET_RESET);

for (loop = 0; loop < 0x10000; loop++);

/* USB 2 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GUSB2PHYCFG_PHYSOFTRST,
DWC_USB_GUSB2PHYCFG_PHYSOFTRST_INACTIVE);

/* USB 3 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GUSB3PIPECTL_PHYSOFTRST,
DWC_USB_GUSB3PIPECTL_PHYSOFTRST_INACTIVE);

for (loop = 0; loop < 0x10000; loop++);

/* USB 3 PHY Reset */
HW_WR_FIELD32(dwc3BaseAddr,
DWC_USB_GCTL_CORESOFTRESET,
DWC_USB_GCTL_CORESOFTRESET_NO);

}

Regards, Eric

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Can't enable USB1_DRVVBUS on AM572x IDK