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Hardware watchpoint doesn't trigger in NAND boot

Bruce McKinley
Intellectual 760 points

Hi,

I have the K2H set up for NAND boot by placing 0x106E7 in DEVSTAT. I create a H/W watchpoint on read from 0x30000000 which is where NAND flash resides. I enable "Halt on Reset, then I reset the CPU. The PC goes to 0x00000000. Everything should be good. Then I run, but the H/W watchpoint never triggers, and the PC ends up in a loop at 0x000009D8. That is the same address as it end up in "No Boot" mode.


Please help!


Thanks,
Bruce

  • 0
    TI__Guru** 116170 points

    Bruce,

    Only NOR flash connected to EMIF16 is direct addressable using the memory space starting 0x30000000. NAND flash has its own geometry in form of blocks, pages and rows and columns and NAND flash needs to be accessed in reference to its geometry so direct address will not work in accessing the NAND. The PC seems to be at ARM ROM memory location. have you flashed anything in the NAND flash?

    For programming the NAND, please refer to the NAND writer code in our MCSDK or Processor SDK RTOS to take a look at how NAND memory is accessed with ECC support enabled.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 760 points
    I understand that we can't direct access the NAND flash because of the protocol. However, I am trying to set up a H/W breakpoint for any read from 0x30000000 so that the RBL will be interrupted during a NAND flash boot.
  • 0 in reply to Bruce McKinley
    TI__Guru** 116170 points

    In NAND memories, read and write operations happen on a per page basis, but erase operations happen per block. Also The NAND flash has a single bus for sending command and address information as well as for sending and receiving memory contents.  Can you specify how you are setting the hardware break point ?

    I tried this on my local setup but couldn`t hit the break point but if I do access 0x3000_0000 during a read access to check if it is an ONFI NAND, I can see the characters "O", "N", "F", "I" as you can se from screenshot below:

    You can also reproduce this by setting hardware break point at address 0x0005E48.

    Regards,

    Rahul

    PS: You can use the NAND read code provided in the bootROM for C665x device for reference.

     

    K2H and C6655 have the same EMIF16 interface  so the K2H ROM  NAND boot code is based of the same code base.

  • 0 in reply to Rahul Prabhu
    Intellectual 760 points
    Yes, the processor does access NAND at instruction 0x0005E48. I was able to get the watchpoint to trigger at Read from 0x3000_0000 as well.

    The problem we had been running into is that single-stepping with the emulator (F6) across certain function calls in the RBL causes the program to fail and loop forever at 0x128 . That's why we never hit the watchpoint. We we ran (F8) instead of single-stepping (F6) we were able to break at all instructions reading from NAND at 0x3000_0000.