c6474 emacboot problem

Have you iniitialized the PHY. It will be useful if you can explain the setup a bit.

Thanks,

Arun.

Hi,

 I tried to do the EMAC booting in TMS320C6474 EVM, where initial level bootloader is from I2CEPROM(same is attached). The I2CEPROM is programmed by modifying the I2C_example program given in the CD.I verified the data by reading the I2C Eprom .But after changing the bootmode to I2C master mode ,I am not able to see the ethernet ready frame .Also the booting process is not happening after sending the bootpacket to processor from a PC.I verified the frame in Etherral.

Regards,

ocv.

The PHY initialization goes out of sync and the BOOTP packet is generated before the PHY is initalized. Add the delay below in the PHY config table and try.

0x10885F00
0x40000000  /* Set up delay: about 3.82 seconds */
0xBFFFFFFF

Hi,

I tried the same.Still it's not working.I hope EVM version(using version D) and the initial bootloader's  are not the  issue.

Hi,ArunMani,the delay func is a func in the rom code ?It seemed did not work after i add the address.  

I SET GPIO 1 AND 3 HIGH TO SHOW THE TABLE IS READ BY THE BOOT CODE  
Uint8 boot_config[160] =    // Always big endian
{
    0x00, 0xa0, 0x00, 0x00,  // Len / Checksum
  
	  0x02, 0xb0, 0x00, 0x10,  //  set gpio output
    0x00, 0x00, 0x00, 0x00,  // Set
    0xff, 0xff, 0xff, 0xff,  // Clear
    
    0x02, 0xb0, 0x00, 0x14,  // set gpio 1 3 high
    0x00, 0x00, 0x00, 0xf5,  // Set
    0xff, 0xff, 0xff, 0xfa,  // Clear
    
    0x02, 0xc8, 0x18, 0x04,   //mdio reset
    0x40, 0x00, 0x00, 0x1f,   //set
    0xbf, 0xff, 0xff, 0xe0,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 set phy address
    0xc0, 0x9b, 0x00, 0x81,    //set
    0x3f, 0x64, 0xff, 0x7e,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 port 6 serdes
    0xc3, 0x4e, 0x00, 0x47,     //set
    0x3c, 0xb1, 0xff, 0xb8,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 port 5 serdes
    0xc4, 0xcd, 0x00, 0x47,     //set
    0x3b, 0x32, 0xff, 0xb8,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 port 6 1000m ,full duplex
    0xc0, 0x0e, 0x81, 0x40,     //set
    0x3f, 0xf1, 0x7e, 0xbf,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 port 5 1000m full duplex
    0xc0, 0x0d, 0x81, 0x40,     //set
    0x3f, 0xf2, 0x7e, 0xbf,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 force internal switch port 6
    0xc0, 0x35, 0x04, 0x3e,     //set
    0x3f, 0xca, 0xfb, 0xc1,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 force internal switch port 5
    0xc0, 0x36, 0x04, 0x3e,     //set
    0x3f, 0xc9, 0xfb, 0xc1,    //nop
    
    0x02, 0xc8, 0x18, 0x80,   //mdio user reg 0 
    0xc0, 0x01, 0xa1, 0x00,     //set
    0x3f, 0xfe, 0x5e, 0xff,    //nop
    
    0x10, 0x88, 0x5f, 0x00,
    0x40, 0x00, 0x00, 0x00,
    0xbf, 0xff, 0xff, 0xff,
   
    0x00, 0x00, 0x00, 0x00,  // Terminator
    0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    
};

Hi,

Same is happening  for me too.DSP is  hanging at the delay function(checked by using the GPIO lines).The PHY is not getting configured after removing the delay function.

Regards,

ocv.

The internal Delay code should work. I tested it.  Only other issue is you board version. I am attaching the errata file link here. There is a issue with ethernet ready packet transmission. They also provide a way to check your board revision. Please let me know if this works for both you guyz.

http://focus.ti.com/docs/prod/folders/print/tms320c6474.html

Thanks,

Arun.

Hi,

It's working for me.I could see theBOOTP packet and able to boot both DSP's.

Address to romArgDelay was not correct in the earlier bootconfig table.

Regards,

ocv.

Hi Arun,

I am working on TMDXEVM6474 and trying to verify port 4 of Marvell PHY routed to Port 0 of AMC edge connector.

Getting a bootp packet via a MicroTCA backplane sounds to the simplest way to do this.

I edited the .ccs file provided by you to configure port 4 SERDES of Marvell PHY. Please find this attached for your reference.

But, after flashing this file to EEPROM, I am unable to get bootp packet either out of RJ45 connector or through AMC backplane. To my surpise the bootp packet is not seen on RJ45 connector also.

Can you please provide any suggestion on getting the bootp packet through AMC ethernet port.

Thanks,

Amit

Hi Amit,

I don't know much about the AMC, but did you check that port4 is indeed connected to the AMC? Also if there is any issue on the boot config table, you might have some problem in completing the configuration. Can you check the file i have attached and see whether you can get the BOOTP packet through the RJ45?

Thanks,

Arun.

Hi Arun,

Thank you for your response.

ArunMani said:

Can you check the file i have attached and see whether you can get the BOOTP packet through the RJ45?

Yes, I am able to get the bootp packet out of RJ45 connector with your EEPROM image.

Using the extra configuration of port 4 of PHY, I am able to perform EMAC loopback on AMC edge port 0.

I have verified the boot config table, and updated the number of lines to read in "dat header" and size as the first word.

Thanks,

Amit