TMS320DM6467T Transport Stream Interface

Refer to the following sections in DM6467T data sheet for more details on TSIF0 pinmux:

4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)

Regards, Srirami.

Hi,

If TS stream interface is going to be synchronous interface, WAIT pin (Used for async interface) can be used as GPIO.

As per Srirami's mail, pin mux needs to be configured accordingly...

Regards,

Nageswari.S

Hello all:

  I am being puzzled about the TS interface a few days,I want to test the parallel,synchronous,and input model of TSIF0,I am not sure whether I only need  the following eleven pins or need some more?

1.TS0_CLKIN(TSIF0 receive clock input )

2.TS0_EN_WAITO(date enable)

3.TS0_PSTIN(packet start)

 4.TSDIN0——TSDIN7(data)

In my opinion, the pin TS0_WAITIN is not needed when the model is synchronous,I don't know whether   some other  I have't consider, the following is my test:

The TSIF interface is on DC_P2 connector on DM6467 , I want to test the parallel,synchronous,and input model of TSIF0, I haved designed a TSIF connector in order to connect the TSIF interface on DC_P2 to another board(a board has the function as TS analyzer),and there only eleven pins:

1.TS0_CLKIN(TSIF0 receive clock input )

2.TS0_EN_WAITO(date enable)

3.TS0_PSTIN(packet start)

 4.TSDIN0——TSDIN7(data)

 The above is my hardware,and I install the TSIF driver,compile the application (saTsifUserPtrBuffer and so on),and I use oscilloscope to measure the above eleven pins,all normal,so The TSIF source is right,it can produce the right TS signal.

But when I execute the application: ./ ./saTsifUserPtrBuffer 60000 60000 60000 60000 ,it only turn out only the followings information:

 -------------------Send the Data from the MPEG2 TS Analyzer

Last,I put some debug information in the TS Driver,I found it can't execute the irqreturn_t tsif_isr(int irq, void *dev_id, struct pt_regs *regs) function, so it can't produce interrupt. The application I have changed some, although I only configure it BYPASS model to receive any packets ,still can't produce interrupt.

Anyone encounter the above question? If some problem is related to my HardWare ?but I think the parallel,synchronous,and input model of TSIF0 only 11 pins,am I right?

Thanks everyone!

hello :

   I want to test the parallel,synchronous,and input model of TSIF0, which pins I need?I think only the following pins is must,am i right?

1.TS0_CLKIN(TSIF0 receive clock input )

2.TS0_EN_WAITO(date enable)

3.TS0_PSTIN(packet start)

 4.TSDIN0——TSDIN7(data)

TS0_WAITIN-pin and TS0_ENAO should need?this is may be asynchronous.right?

If I am right ,but when I test ,I failed.

The TSIF interface is on DC_P2 connector on DM6467 , I want to test the parallel,synchronous,and input model of TSIF0, I haved designed a TSIF connector in order to connect the TSIF interface on DC_P2 to another board(a board has the function as TS analyzer),and there only eleven pins:

1.TS0_CLKIN(TSIF0 receive clock input )

2.TS0_EN_WAITO(date enable)

3.TS0_PSTIN(packet start)

 4.TSDIN0——TSDIN7(data)

 The above is my hardware,and I install the TSIF driver,compile the application (saTsifUserPtrBuffer and so on),and I use oscilloscope to measure the above eleven pins,all normal,so The TSIF source is right,it can produce the right TS signal.

But when I execute the application: ./ ./saTsifUserPtrBuffer 60000 60000 60000 60000 ,it only turn out only the followings information:

 -------------------Send the Data from the MPEG2 TS Analyzer

Last,I put some debug information in the TS Driver,I found it can't execute the irqreturn_t tsif_isr(int irq, void *dev_id, struct pt_regs *regs) function, so it can't produce interrupt. The application I have changed some, although I only configure it BYPASS model to receive any packets ,still can't produce interrupt.

Anyone encounter the above question? If some problem is related to my HardWare ?but I think the parallel,synchronous,and input model of TSIF0 only 11 pins,am I right?

thank you .

I am looking forward to your answer.

hello all:

  What  kinds of Time requirements should  need for TSIF0 interface  when  receiving data  in the model of parallel,synchronous,and Non-TS Packets,what condition should satisfy for the following signals ?

1.TS0_CLKIN(TSIF0 receive clock input )

2.TS0_EN_WAITO(date enable)

3.TS0_PSTIN(packet start)

 4.TSDIN0——TSDIN7(data)

 thanks in Thanks in advance.