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OMAP3530 L2 Cache - non Linux

Jason Vorel36
Intellectual 1500 points
Other Parts Discussed in Thread: OMAP3530

I have read many postings from TI, Beagle, and ARM.  Most postings talked about enabling the L2 cache in the Linux kernel.  We are developing our own OS, so those postings do not help.

 

In chapter 8 of the Cortex A8 TRM, I saw instructions to enable and disable the L2 cache.  I followed those instructions without success. 

I just have a few questions about the L2 cache on OMAP3530:

1)      After reset, there really isn't anything needed to be done with clock and power domains to enable the L2 Cache SRAM?

2)      First I am disabling L2 cache before I try to enable it.  Do I need to wait between disabling cache and enabling cache?

3)      Are isb instructions needed after any step for synchronization?

 

 

  • 0
    TI__Expert 5960 points

    Hi Jason,

    Below is some assembly code take from a stand alone (no OS) C project.  This code is taken from boot.asm which is the boot code which runs on processor reset. I did not copy everything to this forum page, but basically the boot code puts the ARM into supervisor mode and sets up the C stack and the MMU, then it enables the L1 and L2 cache. If done at reset, I don't think you need to disable L2 or any "ISB" instructions are needed.  Do you also need to turn on and off L2 interactively  or just a reset?

    ;------------------------------------------------------

    ;* ENABLE INSTRUCTION AND DATA CACHE, Branch Prediction

    ;*------------------------------------------------------

    .if __TI_TMS470_V7__

    MRC p15, #0, r0, c1, c0, #0

    ORR r0, r0, #(0x1 << 12) ; enable I Cache

    ORR r0, r0, #(0x1 << 11) ; enable branch prediction

    ORR r0, r0, #(0x1 << 2) ; enable D Cache

    BIC r0, r0, #(0x1 << 1) ; disable alignment checks

    MCR p15, #0, r0, c1, c0, #0

    ;/Enable L2 Cache */

    MRC p15, #0, R0, c1, c0, #1 ;/* Read Auxiliary Control Register */

    MOV R1, #0x02

    ORR R0, R1, R0 ; /* Set L2EN bit */

    MCR p15, #0, R0, c1, c0, #1 ; /* Enable L2$ */

    .endif

  • 0 in reply to Jeff L
    Intellectual 895 points

    Hi Jeff

    I am using Code Composer v4.2.1 for the OMAP35. When i run software update, it tells me that everything is up to date.
    However, my boot.asm looks different than yours! How come?

    C:\Program Files (x86)\Texas Instruments\ccsv4\tools\compiler\TMS470 Code Generation Tools 4.6.4\lib\rtssrc.zip

    Altough the D Cache is not enabled until you enable the MMU, that's whats written in the ARM Infocenter..
    Why must I enable the MMU to use the D-Cache but not for the I-Cache: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka13835.html

     

  • 0 in reply to MGun
    TI__Expert 5960 points

    Hi,

    The snippet provided was from 3+ years ago. It was a stand alone project which performed some minimal setup including MMU and cache. It was not a robust boot.asm. As you pointed out only the cache portion of the setup was shown in the wiki article.  What you have is much more up to date.

  • 0 in reply to Jeff L
    Intellectual 895 points

    Thanks Jeff. But you noticed that the ARM is extremly slow without D-Cache enabled?
    http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/93065.aspx

    Can you give me some information what has to be done to enable the D-Cache with the MMU? Do i need virtual adresses for all the peripheral (e.g. Timers?)

  • 0 in reply to MGun
    TI__Expert 5960 points

    MGun,

    Sorry I was not aware of your previous post.  I will start addressing you previous post and get back to this one. I don't think you should need virtual addresses assigned.

    My team focuses mainly on Linux, but I will still try to answer your questions.