The configuration of OMAP-L137 for Burst Transfer Mode

Wang Yu 14

Other Parts Discussed in Thread: OMAPL138

Hi,

I'm using OMAPL137 for audio project. I want to configure the McASP as Burst Transfer Mode and the AIC3106 as DSP Mode, so I can get left and right sample at one slot. The slot size is 32 bit and each channel is 16 bit. I want to get the data using transmit interrupt so when every interrupt occurs, I get acquire two channel signals and drive two channel loudspeakers. The code is modified from TI example routines and copied as follows. The question is when I stored the input samples in a buffer I can't get correct data from microphones. I have no idea what's wrong with it.

EVMC6747_AIC3106_rset( 3, 0x22 ); // 3 PLL A <- [PLL=OFF][Q=4][P=2]
EVMC6747_AIC3106_rset( 4, 0x20 ); // 4 PLL B <- [J=8]
EVMC6747_AIC3106_rset( 5, 0x6E ); // 5 PLL C <- [D=7075]
EVMC6747_AIC3106_rset( 6, 0x23 ); // 6 PLL D <- [D=7075]
EVMC6747_AIC3106_rset( 7, 0x0A ); // 7 Codec Datapath Setup <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
EVMC6747_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A <- [BCLK=Slave][MCLK=Slave]
EVMC6747_AIC3106_rset( 9, 0x40 ); // 9 Audio Interface Control B <- [DSP mode][16 bit]
EVMC6747_AIC3106_rset( 10, 0x00 ); // 10 Audio Interface Control C <- [Data offset=0]
EVMC6747_AIC3106_rset( 15, 0x30 ); // 15 Left ADC PGA Gain <- [Mute=OFF] [PGA Gain=24dB]
EVMC6747_AIC3106_rset( 16, 0x30 ); // 16 Right ADC PGA Gain <- [Mute=OFF] [PGA Gain=24dB]
EVMC6747_AIC3106_rset( 19, 0x04 ); // 19 LINE1L to Left ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
EVMC6747_AIC3106_rset( 22, 0x04 ); // 22 LINE1R to Right ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
EVMC6747_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
EVMC6747_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
EVMC6747_AIC3106_rset( 43, 0 ); // 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMC6747_AIC3106_rset( 44, 0 ); // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMC6747_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume <- [Routed]
EVMC6747_AIC3106_rset( 51, 0x09 ); // 51 HPLOUT Output <- [Mute=OFF][Power=ON]
EVMC6747_AIC3106_rset( 58, 0 ); // 58 HPLCOM Output <- []
EVMC6747_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume <- [Routed]
EVMC6747_AIC3106_rset( 65, 0x09 ); // 65 HPROUT Output <- [Mute=OFF][Power=ON]
EVMC6747_AIC3106_rset( 72, 0 ); // 72 HPRCOM Output <- []
EVMC6747_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume <- [Routed]
EVMC6747_AIC3106_rset( 86, 0x09 ); // 86 LEFT_LOP/M Output <- [Mute=OFF][Power=ON]
EVMC6747_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed]
EVMC6747_AIC3106_rset( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON]
EVMC6747_AIC3106_rset(101, 0x01 ); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT]
EVMC6747_AIC3106_rset(102, 0 ); // 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK]

/* Initialize MCASP1 */
mcasp = &MCASP_MODULE_1;

/* ---------------------------------------------------------------- *
* *
* McASP1 is in MASTER mode. *
* BCLK & WCLK come from McASP1 *
* DIN is used by write16/write32 *
* DOUT is usec by read16/read32 *
* *
* ---------------------------------------------------------------- */
mcasp->regs->GBLCTL = 0; // Reset
mcasp->regs->RGBLCTL = 0; // Reset RX
mcasp->regs->XGBLCTL = 0; // Reset TX
mcasp->regs->PWRDEMU = 1; // Free-running

/* RX */
// configure McASP0 receive registers
mcasp->regs->RMASK = 0xFFFFFFFF; // No padding used
mcasp->regs->RFMT = 0x000080F8; // MSB 32bit, 0-delay, no pad, CFGBus
mcasp->regs->AFSRCTL = 0x00000002; // burst, 1bit Falling, INTERNAL FS, word
mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
mcasp->regs->RTDM = 0x00000001; // Slots 0
mcasp->regs->RINTCTL = 0x00000000; // Not used
mcasp->regs->RCLKCHK = 0x00FF0008; //

// configure McASP0 transmit registers
mcasp->regs->XMASK = 0xFFFFFFFF; // No padding used
mcasp->regs->XFMT = 0x000080F8; // MSB 16bit, 0-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000002; // burst, 1bit Rising, INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp->regs->XTDM = 0x00000001; // slot 0
mcasp->regs->XINTCTL = 0x00000020; // interrupt on transmit
mcasp->regs->XCLKCHK = 0x00FF0008; //

mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT

// config pin function and direction.
mcasp->regs->PFUNC = 0; // All MCASPs
mcasp->regs->PDIR = 0x14000020; // All inputs except AXR1[5], ACLKX1, AFSX1
mcasp->regs->DITCTL = 0x00000000;
mcasp->regs->DLBCTL = 0x00000000;
mcasp->regs->AMUTE = 0x00000000;

/* Starting sections of the McASP*/
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );

mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );

mcasp->regs->XSTAT = 0x0000ffff; // Clear all
mcasp->regs->RSTAT = 0x0000ffff; // Clear all

mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );

/* Write a 0, so that no underrun occurs after releasing the state machine */
mcasp->regs->XBUF5 = 0;
mcasp->regs->RBUF0 = 0;

mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );

mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );

/* Start by sending a dummy write */
while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready
mcasp->regs->XBUF5 = 0;

And the input functions are:

Int32 input_sample(void)
{
AIC31_data.uint = MCASP1_RBUF0_32BIT;
return (AIC31_data.uint);
}

Int16 input_left_sample(void)
{
AIC31_data.uint = MCASP1_RBUF0_32BIT;
return (AIC31_data.channel[LEFT]);
}

Int16 input_right_sample(void)
{
AIC31_data.uint = MCASP1_RBUF0_32BIT;
return (AIC31_data.channel[RIGHT]);
}

I used these codes to store the input sample:

{dn = input_sample();

buffer[bufferptr] = dn;

bufferptr = (bufferptr+1)% 480000;}

Thanks for your guidance!

Best regards,

Wang Yu

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

Please refer the below E2E post and find attached the "7573.OMAPL137_McASP_EDMA_StarterWare.zip” for a working McASP-EDMA audio loopback sample code available for OMAPL137 platform which is ported from OMAPl138. Actually, the sample example below is been modified by taking OMAPL138 McASP Starterware audio loopback example as reference and being modified the pinmux & platform level code changes appropriately to work for OMAPL137 platform.

https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/423721/1512249#1512249

Kindly look for the sample .CCS project path below to look for OMAPL137 McASP EDMA audio loopback example after extracting the above attached zip file:

~\OMAPL137_McASP_EDMA_StarterWare\build\c674x\cgt_ccs\omapl137\evmOMAPL137\mcasp\.ccsproject

Thanks & regards,

Sivaraj K

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Please click the Verify Answer button on this post if it answers your question.

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0 Wang Yu 14 over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 125 points

Hi, Sivaraj K,

Thank you for your reply. I have read the project you supported to me. But I think there are few differences between the routine and my requirement. The code in StarterWare use I2S mode but I need to use DSP mode and I have no idea how to modify the codes. Can you have a look at my program and tell me how to set the value of registers that need to be modified to meet my requirement? I want to configure the McASP as burst transfer mode and AIC3106 as DSP mode. Now I can output sound using left and right channels dependently but can't get the proper signal from microphones.

Maybe I'd better to divide my question into some pieces.

1. When configuring AIC3106, I want to set is as DSP mode, so I modified the 9th registers as 0x40 according to the datasheet and left other register values unchanged. (There is a problem that I want to set the sampling rate as 8000Hz so I modified the second register as 0xAA but the fs didn't change, is there any other registers need to be modify?)

2. About the McASP, the question is how to set the following registers.

XMFT = 0x000080F8 Because of MSB,16bit, 0-delay, no pad and CFGBus;

AFSXCTL = 0x00000002 I need burst mode, rising edge sampling, internal frame sync and single bit;

ACLKXCTL = 0x000000AF Using ASYNC, Rising INTERNAL CLK, div-by-16

AHCLKXCTL = 0x00000000 EXT CLK

XTDM = 0x00000001 Just one slot 0 used

XINTCTL = 0x00000020 I want to get data each interrupt on transmit

XCLKCHK = 0x00000000 According to the datasheet

PDIR = 0x14000020 All inputs except AXR1[5], ACLKX1, AFSX1.

And other registers are set as TI example routine. Is there anything wrong?

3. I can't understand what's the difference between internal and external clock. Can I use any one of these two clocks on the OMAPL137?

4. The input pins are only used as input pin, right? I mean, if I use OMAPL137, the input pins are set in advance and I can't change it as output pin?

Best regards,

Wang Yu

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The configuration of OMAP-L137 for Burst Transfer Mode