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66AK2HK Clocking Issue

vidya krishnamoorthy
Expert 2865 points
Other Parts Discussed in Thread: 66AK2H14

HI,

We have designed board with 66Ak2h14 processor.

I want to the know the  DEVSTAT value to be set in no boot mode and nand boot mode.

In processor datasheet, it is specified that ARM core will act  up to 1.4-GHz Cortex-A15 Processor Core Speed and DSP core up to 1.2 GHz.

But if i read DEVSPEED register it shows all 0's value which means 800Mhz .

How is this possible and is there setting to make processor to achieve high clock speed ?

What is the bootmode value i need to set to DEVSTAT register ?

I want to know what is devstat value i need to set for no boot mode and nand boot mode ?

And also please let me know why devspeed is showing 800Mhz instead of actual speed ?

Please guide,

  • 0
    TI__Guru* 81335 points
    Hi Vidya,

    Please do not create duplicate threads for the same issue/query. We will get back to you shortly. Thank you for your patience.
  • 0
    Guru 92251 points

    vidya krishnamoorthy said:
    But if i read DEVSPEED register it shows all 0's value which means 800Mhz .

    What address are you reading the DEVSPEED register from?

    There is an error in the 66AK2H14 datasheet SPRS866E - see 66AK2H14 datasheet SPRS866E doesn't show that the address of the Device Speed DEVSPEED register depends upon the Silicon Revision

  • 0 in reply to Chester Gillon
    TI__Guru* 81335 points
    Hi Chester,

    Thank you for the post and support to e2e community.
  • 0 in reply to Chester Gillon
    Expert 2865 points

    Hi,

    Thanks for your input.

    I am reading 0x02620c98 DevSpeed register which shows zero value and the processor part number is 66AK2H14AAW

    According to the fig2-1 in your link, maximum dev speed for our device is 1GHZ .

    Please guide at what speed do both ARM and DSP processor will act .Will both act in 1GHZ speed ?

     

  • 0 in reply to vidya krishnamoorthy
    TI__Guru* 81335 points

    Vidya,

    You may be looking at device marking(66AK2H14AAW) not the order-able part number, please refer the packaging information of data manual for correct part number.

    Please read JTAGID register to confirm the SoC revision. Refer below thread.

    Upon confirmation of SoC revision, please read the DEVSPEED to confirm the max dev speed.

    Thank you.

  • 0 in reply to Raja
    Expert 2865 points

    Hi Raja,

    I read the top marking of chip and its shows 1.2Ghz/1.4Ghz..

    Even though it shows 1.2/1.4Ghz , i am able to port the u-boot with dsp core acting at 614mhz and Arm core at 625Mhz.

    If i try to increase the pll, u-boot hangs. I am porting u-boot through ccs and checking with different pll.

    we are programming DEVSTAT (BOOT MODE) values through FPGA during startup.

    If DEVSTAT value is wrong does it affects in processor clock frequency. ?

    I have kept the devstat value as 0x02030aa7 which is working in 614/625 Mhz

    To achieve highest clock frequency, what value do i need to configure in DEVSTAT ?

    Please guide,

  • 0 in reply to vidya krishnamoorthy
    TI__Guru* 81335 points

    If DEVSTAT value is wrong does it affects in processor clock frequency. ?

    Yes. It will affect processor clock frequency.

    I have kept the devstat value as 0x02030aa7 which is working in 614/625 Mhz

    To achieve highest clock frequency, what value do i need to configure in DEVSTAT ?

    https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/393729/1883314#1883314

    I took reference clock frequency from above thread that, ARM - 125MHz and DSP 122.88MHz. As per my understanding, it should operate 590/600MHz respectively. Refer S.No 1 & 2 on below table. How are you measuring the DSP & ARM frequencies?

    You can set the DEVSTAT to 0x02030EE7 for maximum possible frequency configurations. Refer S.No 3 & 4 on below table.

    S.No Board Reference Clock (CLKIN) PLLM PLLD OUTPUT DIVIDE Clock in MHz  Measured? Remarks
    1 K2H - DSP 122.88 47 4 1 589.824 614 101 - The PLLM and PLLD values are taken from Table 8-27 & Table 8-28 of Data manual
    2 K2H - ARM 125 47 4 1 600 625
    3 K2H - DSP 122.88 19 0 1 1228.8 ? 111 - The PLLM and PLLD values are taken from Table 8-27 & Table 8-28 of Data manual. Set the devstat to - 0x02030EE7
    4 K2H - ARM 125 19 0 1 1250 ?

    Thank you.

  • 0 in reply to Raja
    Expert 2865 points

    Hi Raja,

    Thanks for your inputs,

    I have already tried these combination but none works.

    I posted many queries regarding this clocking issue but dint get any  proper answer.  

    At last, i framed the devstat value as 0x02030ac7 and now arm and dsp working at almost 500Mhz.

    This is very low but when i keep this devstat value, our board is stable. When i frame this 0x02030EE7 , board is in continuous reset state.

  • 0 in reply to vidya krishnamoorthy
    TI__Guru* 81335 points
    My suggestion works well on EVM(I have tried) so I do not know what is the issue with your custom board.

    Thank you.