Hello,
The PLL Bypass mode seems to be working right on my DM355 board. But when in PLL bypass mode, the USB subsystem doesn't seem to be OK. For example:
# echo "pllbypass" > /sys/power/state
Now we are in PLL bypass. I have a 3G modem connected to the USB. In normal mode, it works fine. But in PLL bypass mode, if I try to dial out using PPPD:
# pppd &
usb 1-1.1: pppd timed out on ep0out
qcmdm_read_bulk():bulk rx status -2
Failed to open /dev/ttyQCMDM0: Input/output error
Timeout 0xe2dc:0x0 in 30.000 seconds.
# lsusb
Bus 001 Device 005: ID 1c9e:9000
Bus 001 Device 002: ID 058f:6254 Alcor Micro Corp.
Bus 001 Device 001: ID 04d6:0000 Mentor Graphics
The USB modem is there all right (Device 005).
So then I switch back to PLL ON, and I get all these USB related prints. Looks like the USB subsystem gets re-init:
# echo "pllon" > /sys/power/state
kdpdg: PLL1_PLLM(0x8F)
kdpdg: PLL1_PLLM(0x8F)
usb 1-1: USB disconnect, address 2
# usb 1-1.1: USB disconnect, address 5
entering qcmdc_disconnect(), the intferface num is 0
entering qcmdc_disconnect(), the intferface num is 1
entering qcmdm_disconnect(), the intferface num is 3
usb 1-1: new high speed USB device using musb_hdrc and address 6
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
usb 1-1.1: new high speed USB device using musb_hdrc and address 7
usb 1-1.1: Product: USB Modem
usb 1-1.1: Manufacturer: USB Modem
usb 1-1.1: SerialNumber: 1234567890ABCDEF
qcmdc 1-1.1:1.0: ttyQCMDC0: USB QCMDC device
qcmdc 1-1.1:1.1: ttyQCMDC1: USB QCMDC device
scsi1 : SCSI emulation for USB Mass Storage devices
qcmdm 1-1.1:1.3: ttyQCMDM0: USB QCMDM device
usb 1-1.4: new low speed USB device using musb_hdrc and address 8
usb 1-1.4: device descriptor read/64, error -32
usb 1-1.4: device descriptor read/64, error -32
usb 1-1.4: new low speed USB device using musb_hdrc and address 9
usb 1-1.4: device descriptor read/64, error -32
usb 1-1.4: device descriptor read/64, error -32
Vendor: USBModem Model: Disk Rev: 2.31
Type: Direct-Access ANSI SCSI revision: 02
Attached scsi removable disk sda at scsi1, channel 0, id 0, lun 0
So I'm guessing that in PLL BYPASS, the USB was actually non-functional, just that the application layer or the kernel could never properly shut it down. That is why when the PLL is back ON, the USB disconnect is processed properly and then re-initialized.
It makes sense that the USB should not work properly if we are in PLL BYPASS, because in that case the clock driving the peripherials (PLLC1 :: SYSCLK2) would be just 24MHz divided by PLLDIV2 which is fixed to 4. So actually a 6MHz clock is driving the peripherals, including USB. Is that even sufficient to properly drive USB?
There is another clock that can be used to drive the USB, which is the USB-PHY. Do I need to use that clock to drive USB while in PLL BYPASS?
The ARM User Guide (sprufb3.pdf) says in section 5.2.2 that the USB controller is driven by 2 clocks (SYSCLK2 and USB_PHY). Now I'm not quite sure if I understand this right, but we should be able to select one of these to clock sources to drive the USB controller, right?
Thanks and best regards,
Kapil