Hi,
I have a custom board with a AM3352 processor, and I am curently configuring the multiplex settings for each pin, and I've stumbled accross a confusing point when configuring the I/O line for the GPMC module (we are using a MT29F1G08ABADAH4 SLC NAND connected to GPMC):
Should the I/O lines for the GPMC modules be setup as pull up or pull down, or should I disable PU/PD configuration completely? We've theorized that there is no need to configure this, as the memory should drive the lines correctly, but we found no evidence for this on the TRM or our memory's datasheet.
Also, we have the same question regarding the EMIF module.
Regards,
Guilherme