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Pull up/Pull down configuration for memory I/O lines

Guilherme Costa
Intellectual 635 points
Other Parts Discussed in Thread: AM3352

Hi,

I have a custom board with a AM3352 processor, and I am curently configuring the multiplex settings for each pin, and I've stumbled accross a confusing point when configuring the I/O line for the GPMC module (we are using a MT29F1G08ABADAH4 SLC NAND connected to GPMC):

Should the I/O lines for the GPMC modules be setup as pull up or pull down, or should I disable PU/PD configuration completely? We've theorized that there is no need to configure this, as the memory should drive the lines correctly, but we found no evidence for this on the TRM or our memory's datasheet.

Also, we have the same question regarding the EMIF module.

Regards,

Guilherme

 

  • 0
    TI__Guru**** 161600 points
    Hi Guilherme,

    For the GPMC pins, which interface with the nand device, refer to the existing configurations in latest SDK 2.00.02.11 (kernel 4.1.18), resource is board/ti/am335x/mux.c:
    module_pin_mux nand_pin_mux[] => gpmc address data pins (gpmc_ad0 .. gpmc_ad15) are configured with pulls disabled:
    {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}
    And the rest of the gpmc pins are configured as follows:
    {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
    {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
    {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
    {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
    {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
    {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
    {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
    {-1},

    The EMIF (DDR_D0..DDDR_D15) do not have other muxmodes except as DDR_Dx pins, their default state is L (low) (see Table 4-1. Pin Attributes (ZCE and ZCZ Packages) in device data manual), so you shouldn't configure any pulls for them.

    Best Regards,
    Yordan