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DM648 vs. DM647 L2 cache setup

Thomas9070
Expert 1575 points

Hi,

when moving an app from DM647 to DM648,what has to be done to place L2 cache in the 'upper' memory area that is available on the DM647 (0x00A00000-0x00A3FFFF instead of 0x00A00000-0x00A7FFFF)?

is it enough to change the base address of the section CACHE_L2 in the BIOS configuration?

bye,

Thomas

 

  • 0
    TI__Genius 16906 points

    Moved to the BIOS forum for support on what, if anything, in the BIOS configuration needs to change when migrating from DM647 to DM648.

    Regards,

    Brad

  • 0 in reply to B.C.
    TI__Guru*** 125430 points

    Thomas,

    The 64x+ cache architecture supports a mixture of L2 CACHE and SRAM.  However, the maximum amount that can be used as CACHE is 256KB (we actually have some devices that go higher, but not DM647/8).  Therefore what you want to do is just leave the L2_CACHE segment alone (256KB is the max) and then add an additional segment in the MEM section so that you can utilize the upper lower 256KB as SRAM.

    Brad

  • 0 in reply to Brad Griffis
    TI__Mastermind 32475 points

    Thomas,

    I don't think you can change which part of L2 SRAM is cacheable.  The cache should always be at the high address range.

    Brad,

    You can correct me if I'm wrong but I thought if you enable 256K of Cache the high addresses of L2 SRAM (0x00A40000-0x00A7FFFF) would be the Cache and you could use the lower address range (0x00A00000-0x00A3FFFF) as SRAM? 

    Judah

  • 0 in reply to judahvang
    TI__Guru*** 125430 points

    BC,

    We need a reply from the hardware team.  This is no longer a BIOS issue.  The data sheet gives no indication as to how the memories are grouped and what the various cache configurations are.

    On the one hand I agree with Judah that normally RAM is at the beginning, so I think my earlier comment is wrong.  However, I also see last 256k of memory doesn't exist on DM647, so I'm not sure if the cache moves around or what?

    Brad

  • 0 in reply to Brad Griffis
    Expert 1575 points

    Hi Brad and Judah,

    thanks for your answers. In a few days I'll have a DM647 board on my desk and then I'll be able to see whats happening ;-)

    I agree with Judah about the upper/lower end of the L2 SRAM:

    DM648 has 512kB of internal L2 SRAM, DM647 only 256kB. The section of L2 SRAM that is used as L2 Cache is 'in the top end (higher addresses)' of the L2 SRAM. The 'lower end' (starting from 0x00A00000) can be used for any code/data sections of an app ('IRAM').

    A 64kB L2-Cache is located between 0x00A70000 to 0x00A7FFFF on DM648 and 0x00A30000 to 0x00A3FFFF on DM647 (at least this is what I think...). What has to be done to configure the location of the range of L2 SRAM that is used as cache?

    Up to now I have an DM648 app, in the DSP-BIOS configuration ther is :
    IRAM base 0x00A00000 len 0x00070000
    CACHE_L2 base 0x00A70000 len 0x00010000

    Will my application run correctly on an DM647 if I change it to
    IRAM base 0x00A00000 len 0x00030000
    CACHE_L2 base 0x00A30000 len 0x00010000

    bye,

    Thomas

  • 0 in reply to Thomas9070
    TI__Genius 16906 points

    Thomas,

    Yes, your BIOS config looks correct for DM647.  Your app should run correctly as long as it does not need/access more than 192K of L2 SRAM.

    Regards,

    Brad