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AM3505 Power-up sequencing

Kummi
Mastermind 6220 points
Other Parts Discussed in Thread: AM3505, AM3517

Hi,

There is a confusion with AM3505 Power-up sequencing from the datasheet and reference documents.
As per the latest datasheet, the VDDS_DPLL_xx and VDDA1P8V_USBPHY could be ramped up at the same time.



But as per the power reference design and the wiki Design In Guide,
it is mentioned that VDDA1P8V_USBPHY should be ramped after VDDS_DPLL_xx.
http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=68614
http://processors.wiki.ti.com/index.php/AM35x_with_TPS65023:_Design_In_Guide#1.8V_Operation_Sequence


Could you please let us know which one is correct,
can we assume the latest datasheet is the proper one and it is ok to ramp-up simultaneous
and can we use the same 1.8V power source for both VDDS_DPLL_xx and VDDA1P8V_USBPHY?

The wiki has a statement saying
"It is recommended that you combine the voltage source for VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE,
but that source should not power other 1.8V supplies (ie, 1.8V for USB or VDAC) "
http://processors.wiki.ti.com/index.php/AM35x_with_TPS65023:_Design_In_Guide#USB_voltage

Best Regards
Kummi

  • 0
    TI__Guru**** 393215 points
    Hi,

    Please check this document: www.ti.com/.../slva411.pdf It also shows the two 1.8V supplies in question sequenced in different steps, yet there is no delay requirement for them. You can safely follow the datasheet requirements.

    About the VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE question, there are 35mVpp ripple requirements for these supplies, that's why it's recommended that they are tied to a separate voltage source.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points
    Hi Biser,

    Thank you for the quick reply.

    One final confirmation,
    Can we assume it is OK using same 1.8V power source for both VDDS_DPLL_xx and VDDA1P8V_USBPHY?

    Best Regards
    Kummi
  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    You must ensure the ripple voltage requirements are met if you do this.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points

    Hi Biser,

    Thank you very much for the confirmation.

    Please let me ask an additional question on Power-Down Sequence.

    The datasheet mentions that there is no restriction if all the domains are powered down at a time
    "3.Option 1: Power down all domains simultaneously"

    We would like to know if there are any voltage ramp limitations during power down?
    (like voltage difference between the power lines is not allowed..?)

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    No, there are no specific requirements. As a safeguard it would be good to keep voltage difference between 3.3V and 1.8V rails <2V to prevent overstressing the device.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points

    Hi Biser,

    Thank you and I am sorry we have additional question on the sequence.

    Currently our customer is planning to use discrete TI's power ICs for cost reduction.

    As you know the Power-Up sequence don't have specific timing criteria and
    the datasheet mentions each supply should be ramped up to a stable state & then
    the next supply should be ramped up in a sequence.

    We were just wondering will it be OK if we ramp-up next supply while the
    first supply is still ramping up( 50% of its stable state)?

    Can't we apply the Criteria "difference between 3.3V and 1.8V rails <2V" for power-up sequence also?
    In our previous project on AM3517 somewhere we heard that simultaneous sequencing
    could be possible if we ensure a differential of >1v and <2V between 3.3V and 1.8V rails
    but we are not sure on this.

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    I cannot comment what will happen if datasheet requirements are not met, sorry.