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AM335x MPU clock ZCZ to ZCE configuration

Miroslav Bozic
Intellectual 420 points
Other Parts Discussed in Thread: AM3351

Hi,

together with my team I'm working on project that include AM3351.  

For the first prototype we used AM3352BZCZ30 (ZCZ@300MHz) with 19.2 MHZ clk input @ 1V1 core voltage, core clock is set to 300 MHz. Clock configuration for SPL and U-boot is based on the following guide and excel sheet : https://e2e.ti.com/support/arm/sitara_arm/f/791/t/361298. With this setup CPU works fine on 300 MHz.

However, after TI release AM3351 we decide to switch from current solution to the AM3351BZCE60 (ZCE @ 600MHz). We are using same 19.2 MHz clkin and core voltage (1V1). With new processor we found some strange behavior when using the same clock configuration. According to Linux, core freq is 600 MHz (checked with cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq) instead of expected 300 MHz. Also there is very low effective CPU performance comparing with ZCZ@300 MHz even that Linux shows that it ruins on 600 MHz. This is especially noticed with low Ethernet performance and increased context switching time.

Is there any differences regarding cpu core clock settings between ZCZ and ZCE AM335X devices ?

Looking forward to your feedback. 

Regards.

  • 0
    TI__Guru**** 393215 points
    Hi,

    Are you using the same Linux version on both boards? Which version is this? Same DDR memory type and size?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 420 points
    Are you using the same Linux version on both boards? Which version is this?
    Yes we are using same version, Linux 3.14.26 and uboot from SDK 8.0.

    Same DDR memory type and size?
    The memory size is decreased. Previously with AM3352BZCZ30 we used Micron MT41J256M16HA-125:E. For new prototype with AM3351BZCE60 we switch to MT41J128M16JT-125:K TR.

    Regards.
  • 0 in reply to Miroslav Bozic
    TI__Guru**** 393215 points
    I don't think that memory size would cause this issue. As for MPU frequency, Linux kernel recognizes the device type and configures the MPU clock accordingly. One possible reason could be DFVS. could you check your configuration against this guide: processors.wiki.ti.com/.../Linux_Core_Power_Management_User's_Guide_(v3.14)
  • 0
    TI__Guru*** 125430 points

    Miroslav Bozic said:
    For the first prototype we used AM3352BZCZ30 (ZCZ@300MHz) with 19.2 MHZ clk input @ 1V1 core voltage, core clock is set to 300 MHz.

    Are you saying the XTALIN input is a 1.1V signal?  If so, that's not correct.  The pin XTALIN belongs to the power domain VDDS_OSC which is a 1.8V rail.

  • 0 in reply to Brad Griffis
    Intellectual 420 points

    Brad Griffis said:

    Miroslav Bozic
    For the first prototype we used AM3352BZCZ30 (ZCZ@300MHz) with 19.2 MHZ clk input @ 1V1 core voltage, core clock is set to 300 MHz.

    Are you saying the XTALIN input is a 1.1V signal?  If so, that's not correct.  The pin XTALIN belongs to the power domain VDDS_OSC which is a 1.8V rail.

    19.2MHz passive crystal  is used so that is not the problem. Also on AM3352BZCZ30 we didn't have a problem. I will check configuration that Biser proposed and back here with results.

    Thank for your help.

  • 0 in reply to Miroslav Bozic
    Intellectual 420 points
    Hi,
    After more research, we have found that the "scaling_governog" is set to "performance" by default, and that is why we get 600MHz after boot. We are able to switch the governor to "userspace" and set the desired CPU speed to 300MHz. So that is fin now, it seems that everything works as expected.

    Low Ethernet performance on boot from LAN is definitely not related to the CPU speed when it is run Linux, but might be a problem in uBoot.

    Regards.