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AM335x reset occurs with multimeter

Other Parts Discussed in Thread: AM3352, TPS650250

Hello,

I am using currently next configuration:

- AM3352ZCE is powered from PMIC TPS650250RHB.

- The TPS650250 produces all necessary voltages for AM3352.

- Output PWFAIL# (Pin21) is connected to the PWRONRST# (Ball E15) of AM3352. This "RESET" line has a Pull-up resistor 10K to 1.8V  (VDDS)  

Reset of AM3352 occurs always when I want to check voltage on the "RESET" line. It is enough to touch the RESET line  with multimeters test probes in order to initiate reset sequence.

Has anyone experienced with similar Situation?

Thanks.

Br,

Josko

  • Hi,

    I would suggest that you check your multimeter. You can also decrease the value of the pullup resistor or tie it to 3.3V.
  • Hi,

    I have already tried with two different multimeters (Fluke 177 and Keysight U1252B) and with 1K Pull-up resistor and there is no difference.

    Regarding the 3.3V reset line connection, the Situation is as follows:

    - We don't use RTC (Disabled) and our RTC_PWRONRSTn is currently connected also with PWFAIL#(PWRONRST#) Output from PMIC.

    - TI states hier : processors.wiki.ti.com/.../AM335x_Schematic_Checklist
    "RTC_PWRONRSTn high level must be 1.8V. It cannot be 3.3V. If tied together with PWRONRSTn, both reset inputs high level must be 1.8V"

    When the RTC_PWRONRSTn is to GND (VSSS) connected (guidline from same schematich check list), than System will not start boot sequence at all (there is no any traffic or answer on the Serial debug port).

    Besides that, both reference Manual and Datasheet have opposite statements:

    www.ti.com/.../spruh73
    „8.1.4.3.6 Internal RTC LDO“ says: „If your application never uses the RTC functionality, connect RTC_KALDO_ENn to VDDS_RTC, CAP_VDD_RTC to VDD_CORE, and RTC_PWRONRSTn to ground.”

    .www.ti.com/.../am3352
    „Figure 6-5. Power-Supply Sequencing With Internal RTC LDO Disabled“ says:
    “RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.”

    Br,
    Josko
  • For RTC disabled you must have ALL the connections tied as stated in this table in the "RTC feature disabled" column: processors.wiki.ti.com/.../AM335x_Schematic_Checklist

    I can't say what is the problem. I am afraid there may be errors in your design.
  • Thank's on answer. I hope that I will find error.

    I have connected all RTC related pins according to the "RTC Feature disabled" column and than another problem is occured.
    Proccesor will not start with uBoot at all.
    It menas:
    - I have SD Card with configuration and Uboot.
    - When the line RTC_PWRONRSTn is with line PWRONRSTn together tied, system starts normaly (GUI, all control activites on peripheral - LCD, USB, LAN, GPIO,...)
    - When the line RTC_PWRONRSTn is to GND tied and SD Card inserted, nothing has happend. Seems like processor has stucked somewhere becuase there is nothing on the Serial Debug port.
    - When the line RTC_PWRONRSTn is to GND tied and SD Card ejected, I recieve CCCC... stream on Serial Debug Port..

    For now I have watched only activity on Serial Debug port. Haven't checked with JTAG.

    Could you suggest me what is necessary to do in FW/Configuration when "RTC Feature disabled" mode is used?

    Additional question: From HW side, what else can cause processore reset except PWRONRSTn line pulled low?

    Br,
    Josko
  • Can you tell me what your SYSBOOT configuration is? Hardware reset can only happen on the PWRONRSTn or WARMRESETn pins.
  • SYSBOOT[4:0] : 10111: MMC0 -> SPI0 -> UART0 -> USB0
  • OK, this sounds like you have some RTC related initialization in your SPL, that you haven't removed. When the RTC reset is tied to the power-on reset this initialization passes. When RTC reset is grounded this very likely hangs in an endless loop, very likely waiting for a flag to set. I suggest you check the SPL sources and comment out the RTC related initialization from it.
  • Many thanks!

    I will announce results afterwards.

    Br,
    Josko
  • Additional Informations regarding reset by DMM multimeter:
    The same thing occurs when DMM is connected to WARMRSTn pin.

    I found one more difference regarding JTAG. Pins EMU0 and EMU1 have been used as GPIOs Pins and therefore they don't have 4.7K Pull-ups.
    Can that have any influence?
  • The 4.7k pullups on EMU0/1 are strongly recommended. There is an Errata Advisory 1.0.36 regarding these pins usage as GPIO.
  • In my design, I drive the PWRONRST with a push/pull signal to 3.3V.
    The RTC_PWRONRST is driven by a 2K2+2K2 voltage divider tied to PWRONRST.
    THe voltage divider acts as a logic level converter.
    Driving PWRONRST only with 1.8V is not save, because of the unsafe operating area.

    regards
    Wolfgang
  • Hi Wolfgang,

    Thanks on your hint.

    If I have understood well, it is better to drive PWRONRSTn input with push/pull output instead of open collector with pullup? I am using currently the same connection diagram as it has been used in tidr436 (http://www.ti.com/tool/tiep-smart-energy-gateway).

    Does it means that I should provide a buffer tied to 3.3V between PWRONRSTn [E15] and  #POWERFAIL[21]?

    Actually, Focus on Reset signal had been escalated  during ESD testing.

    Br,

    Josko

     

  • Hi Biser,

    an update in meantime:

    1. Same behaviour of my system is for both pins, PWRONRSTn and WARMRSTn when the DMM is connected.

    2. I found out that my deisgin is exactly same as like as design:  tidr436 (http://www.ti.com/tool/tiep-smart-energy-gateway). The PMIC TPS650250, Sitara AM3352BZCE  and Connection between PMIC and Sitara between PWRONRSTn [E15] and  #POWERFAIL[21] are same. If you could ask someone to try the same with DMM on this EVK?

    3. I can noticed that in tidr436 has used 1.8V for pull-up connection on PWRONRSTn line.

    4. Could you find out why they have used 10uF and 0.1uF (C119 and C120) on the RST pin of ETH PHY?

    Br,

    Josko

  • These reference designs are covered by a separate team on a different forum: e2e.ti.com/.../1009 Please ask there.
  • Your DMM has some input capacitance (up so several 100pF). So if you tip the reset line with the DMM probe, you effectively attach a discharged capacitance to the signal which results in a glitch with digital "0" level, causing the reset.
    If you want to measure the absolute voltage level, solder a resistor on your board at the signal you want to measure and measure the voltage at the other end of this resistor. The resistor should be about one magnitude higher than the pull up resistor of the signal you want to measure (normally this will result in a resistor value low enough in order not to interact with your DMMs input resistance).
    When the signal traces get longer, you will also get some susceptibility for nearby ESD events. A small capacitor (100pF...1nF) at the reset line near the processor input to GND can help there.

    tom
  • You have 2 problems here.


    a) PWRONRSTn is a 3.3 Volt Input. You should not drive this input with a 1.8V signal. For example, if the switching point of this input is 3.3V/2 = 1.65V,

    there is a safety margin of 1.8V-1.65V = 0.15V for the HIGH level if driven with 1,8V. This safety margin is too low, and every design with such a low safety margin has a problem.

    So, drive PWRONRSTn with a 3.3V signal.

    b) ESD testing is doing very fast transient signals. If you drive an input signal (for example PWRONRSTn) with a push/pull driver, the PWRONRSTn wire has a very low impedance (maybe 10-20 Ohm), making this input very immune against fast transients.

    If you pullup PWRONRSTn with a 10KOhm Resistor, the impedance is a factor of 1000 times higher, making the input respond to fast transients.

    You have 2 Options to give an input low impedance:

    1) drive the input with a push/pull driver.

    2) add a small capacitor from the input to GND. Use 1-10nF.

    A working solution:

    - PWRONRSTn connected to PWFAIL# (remove the 10KOhm to 1.8Volt)

    - PWRONRSTn to 3.3V with a 1Kohm Pullup

    - PWRONRST to RTC_PWRONRST with 1 KOhm

    - RTC_PWRONRST to GND with 2.2 KOhm.

    - PWRONRSTn to GND with 1-10nF

    - RTC_PWRONRST to GND with 1-10nF

    This solution works without a buffer, but has the disadvantage that there is a steady current of 780uA because of the resistors.

    Patch one of your boards and try it out.

  • Hi Wolfang!

    Thanks on extraordinary advices!

    a) Yes, you have right for HI Voltage input safe margin.
    Actually, I have been confused regarding following:
    - AM335x data sheet, page 90, chapter 5.7: VIH = 1.35V, and leakage current has been defined for VI=1.8V and VI=3.3V.
    - In many reference designs and application notes this reset line has been tied up with pull-up to 1.8V
    - on the wiki Webseite, AM335x_Schematic_Checklist: there is note 5 for RTC: "RTC_PWRONRSTn high level must be 1.8V. It cannot be 3.3V. If tied together with PWRONRSTn, both reset inputs high level must be 1.8V".
    - ...
    - in my design, actually we don't use RTC from Sitara at all, which means that the RTC_PWRONRST# line should be connected to GND and than I don't need 1.8V on the RTC_PWRONRST# line at all. (Reference manual: "8.1.4.3.6 Internal RTC LDO"). Problem is that configuration has a bug where System would not start with booting when this line is to GND connected.

    b)
    Actually, I have already tried 10nF between PWRONRSTn and GND before I asked on this Forum, but it hadn't helped. Additionally had I tried with ESD Diode and ferrite bead on the PWRONRSTn Input.

    I assume that I have problem on WARMRSTn Input becuse this line can also cause HW reset of Sitara. This line has been used as reset output for ETH PHY, eMMC, delayed Whatchdog circuti reset and optional line on AUX connector. The lenght of line is not neglectable, 5 cm verticaly and 10 cm horizontaly. I will place capactitor 1-10nF on this line too.


    1) When I drive PWRONRSTn Input with push/pull Driver, nevertheless I need pull-up before driver?
    2) I will try this of course.

    Br,
    Josko
  • Wolfgang,

    The PWRONRSTn input is compatible with 1.8 volt input with a VIH min of 1.35 volts. This was done to allow both reset inputs to be connected to a 1.8 volt source. However, you are correct a 3.3 volt source would provide more noise immunity.

    Josko,

    The capacitor placement on the signal is very important. It should be located near the reset pin to reduce the impedance of the signal trace at the processor pin. If the capacitor is placed on the far end of the signal, noise will induce current into the signal trace and cause the reset pin to see a voltage transient since this end is still high impedance.

    Regards,
    Paul

  • Hi,

    short feedback about this topic:

    - "RTC Disabled Feature": the problem was in the uBoot-Bootloader and Kernel (were not clean of RTC commands),  because some commands was still there althought the RTC had  not been used.


    - "Reset Durring ESD pulsese": the capacitors 1nF in parallel and ferrite bead in serie on the warm reset and power on reset inputs have helped. I have also used additional ESD diodes on the reset lines and some Cy capacitors on the open drain outputs for inductive valves, but I hadn't had time to prove how much have these realy helped.

    - "Wrong readings on the QEP_A/_B during ESD" - this problem was like the previous and I can confirm that here CY capcitors on both QEP Inputs have helped. 

    All capacitors were placed on the distance 0.5 -1cm from Sitara's package (modification on existing PCB).

    Thanks again on the tips and help.

    Br,

    Josko