Hi，
My customizing board is based on AM5728.
There is 2GB external DDR3 without ECC as memory. 1G connected to EMIF1, and anothor 1G connected
to EMIF2 interface.
I have followed this link http://www.ti.com/lit/an/sprac36/sprac36.pdf
to tuning the DDR3 timing.
I will ask 3 questions:
Question 1:
After that, the EMIF tools generated the code at Register Values table , And I copy it to a file as attchment:
/* =========================================================================
* Copyright (C) 2015 Texas Instruments Incorporated
*
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
* The program may not be used without the written permission
* of Texas Instruments Incorporated or against the terms and conditions
* stipulated in the agreement under which this program has been
* supplied.
* ========================================================================= */
/*
* AM571x_DDR3L_532MHz_TI_EVM_config.c
* Created on: 05/31/2016
* Created with: EMIF_RegisterConfig_v1.0.0
*/
#include "emif4d5_wrapper.h"
const struct dpll_params AM571x_DDR3L_532MHz_TI_EVM_pll_params = {
.m = 266,
.n = 4,
.m2 = 2,
.m4_h11 = 8
};
const struct ctrl_ioregs AM571x_DDR3L_532MHz_TI_EVM_ctrl_ioregs = {
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrch = 0x40404040,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_emif_sdram_config_ext = 0x0000C123
};
const struct dmm_lisa_map_regs AM571x_DDR3L_532MHz_TI_EVM_dmm_regs = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80500100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const struct emif_regs AM571x_DDR3L_532MHz_TI_EVM_emif_regs = {
.sdram_config_init = 0x61851AB2,
.sdram_config = 0x61851AB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x305A7FDA,
.sdram_tim3 = 0x407F8558,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_rd_wr_exec_thresh = 0x00000305
};
/*
* DLL Ratio Values are an estimate based on trace lengths. Either
* software leveling or hardware leveling should be performed to
* determine final DLL values.
*/
const unsigned int AM571x_DDR3L_532MHz_TI_EVM_emif1_ext_phy_regs [] = {
, // EMIF1_EXT_PHY_CTRL_1
, // EMIF1_EXT_PHY_CTRL_2
, // EMIF1_EXT_PHY_CTRL_3
, // EMIF1_EXT_PHY_CTRL_4
, // EMIF1_EXT_PHY_CTRL_5
, // EMIF1_EXT_PHY_CTRL_6
, // EMIF1_EXT_PHY_CTRL_7
, // EMIF1_EXT_PHY_CTRL_8
, // EMIF1_EXT_PHY_CTRL_9
, // EMIF1_EXT_PHY_CTRL_10
, // EMIF1_EXT_PHY_CTRL_11
, // EMIF1_EXT_PHY_CTRL_12
, // EMIF1_EXT_PHY_CTRL_13
, // EMIF1_EXT_PHY_CTRL_14
, // EMIF1_EXT_PHY_CTRL_15
, // EMIF1_EXT_PHY_CTRL_16
, // EMIF1_EXT_PHY_CTRL_17
, // EMIF1_EXT_PHY_CTRL_18
, // EMIF1_EXT_PHY_CTRL_19
, // EMIF1_EXT_PHY_CTRL_20
, // EMIF1_EXT_PHY_CTRL_21
, // EMIF1_EXT_PHY_CTRL_22
, // EMIF1_EXT_PHY_CTRL_23
, // EMIF1_EXT_PHY_CTRL_24
, // EMIF1_EXT_PHY_CTRL_25
, // EMIF1_EXT_PHY_CTRL_26
, // EMIF1_EXT_PHY_CTRL_27
, // EMIF1_EXT_PHY_CTRL_28
, // EMIF1_EXT_PHY_CTRL_29
, // EMIF1_EXT_PHY_CTRL_30
, // EMIF1_EXT_PHY_CTRL_31
, // EMIF1_EXT_PHY_CTRL_32
, // EMIF1_EXT_PHY_CTRL_33
, // EMIF1_EXT_PHY_CTRL_34
, // EMIF1_EXT_PHY_CTRL_35
// EMIF1_EXT_PHY_CTRL_36
};
struct emif_cfg AM571x_DDR3L_532MHz_TI_EVM = {
.platform = "AM571x_DDR3L_532MHz_TI_EVM",
.EMIF2_DEFINED = 0,
.pll_regs = &AM571x_DDR3L_532MHz_TI_EVM_pll_params,
.ctrl_regs = &AM571x_DDR3L_532MHz_TI_EVM_ctrl_ioregs,
.dmm_regs = &AM571x_DDR3L_532MHz_TI_EVM_dmm_regs,
.regs = &AM571x_DDR3L_532MHz_TI_EVM_emif_regs,
.phy_regs1 = AM571x_DDR3L_532MHz_TI_EVM_emif1_ext_phy_regs,
};
I check the uboot source code, and found that just only the following variable needs to be added into uboot source code:
1) lisa_map_regs: AM571x_DDR3L_532MHz_TI_EVM_dmm_regs
2) emif_regs: AM571x_DDR3L_532MHz_TI_EVM_emif_regs
3) AM571x_DDR3L_532MHz_TI_EVM_emif1_ext_phy_regs
is right ? (Because I found just these variable only in $(U-boot)/board/ti/am57xx/board.c, others are located
non board directory. It means that there is no need to modify other variables )
if not, please tell me the following details step for tuning DDR timing, Thank you very much !
=======================================================================================
Question 2:
I found that the AM571x_DDR3L_532MHz_TI_EVM_emif1_ext_phy_regs array is empty, and how can I
determine these final values?
I have seen the note as follow:
"/*
* DLL Ratio Values are an estimate based on trace lengths. Either
* software leveling or hardware leveling should be performed to
* determine final DLL values.
*/ "
But I don't know what is the software leveling or hardware leveling, I see the function omap5_ddr3_leveling in
$(U-boot)/arch/arm/cpu/armv7/omap-common/emif-common.c. it is hardware leveling ?
and the EMIF tools is softleveling ?
Can you give me any other documents/links to describe it ?
Thank you very much again!
Question 3:
When finshed tuning DDR3 timing, how can I determine that the DDR performance is most perfect currently?
Do you has any tools?
Thank you very much again and again !
Best Regards
Qing
