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AM437x: DDR ODT dynamic vs static

Gunter Schmer
Genius 14222 points

Hi,

a customer AM437x design is using the same 2x 16-bit DDR3 configuration as is on the AM437x Starterkit and AM437x IDK. We would like to know how we best arrive at the right DDR side ODT.

[] Is dynamic ODT recommended over static ODT, if the nominal ODT is RZQ/4 or RZQ/2? I am assuming these dynamic values are spec'ed by the DDR vendor ...

[] Is dynamic truly mutually exclusive to static ODT, i.e. the static settings in DDR_TERM have no effect, if DYN_ODT is set?

[] The GEL DDR configuration for the SK and IDK are using static ODT RZQ/6 (40 Ohm). How did we arrive at this setting, as it relates to the 2x 16-bit DDR3 device configuration?

Here is the GEL:

This one is for GP EVM with 4x 8-bit DDR3 devices

#define DDR3_SDRAM_CONFIG       0x61A013B2  //32-bit DDR3
           //differential DQS
           //ODT set to RZQ/4; Dynamic ODT set to RZQ/4
           //drive strength = RZQ/6
           //CWL = 5  400MHz
           //CL = 6   400MHz
           //7 = 16 row bits
           //2 = 10 column bits
           //1 chip select

This one is for SK and IDK with 2x 16-bit DDR3 devices.


#define IDK_EVM_DDR3_SDRAM_CONFIG     0x61A11B32  //32-bit DDR3
              //termination = RZQ/6
              //differential DQS
              //dynamic ODT off
              //drive strength = RZQ/6 (lower drive strength for IDK
              //CWL = 5
              //CL = 6
              //7 = 16 row bits
              //2 = 10 column bits
              //1 chip select

Thanks,

--Gunter

  • 0
    TI__Guru**** 393215 points
    Hi Gunter,

    This is the recommended procedure for AM437x DDR configuration: processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide I will ask the DDR experts to comment on your questions.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 14222 points

    Hi Biser,

    right, we know this wiki. But we would need more specific answers to the questions, the wiki is too general there.

    Thanks,

    --Gunter

  • 0 in reply to Gunter Schmer
    TI__Guru**** 393215 points
    I have notified the DDR experts last time and sent a reminder just now. They will post directly here.
  • 0
    TI__Genius 9655 points

    Gunter,

    Answers below

    Gunter Schmer said:

    [] Is dynamic ODT recommended over static ODT, if the nominal ODT is RZQ/4 or RZQ/2? I am assuming these dynamic values are spec'ed by the DDR vendor ...

    There are 2 different ODT settings on the DRAM. The Rtt_Nom (your reference to Static ODT) and Rtt_WR (dynamic ODT). Rtt_Nom if enabled, is used to terminate the Data lines during idle conditions and during Write operations if Rtt_WR (dynamic ODT) is not set. Rtt_WR is only set during WRITE operation. If Rtt_WR is set along with Rtt_Nom then the memory switches the ODT setting from Rtt_Nom to Rtt_WR value dynamically. The best setting is ideally derived by performing signal integrity simulations. In general, I would suggest that for lower power operation, it is preferable to just set the Rtt_WR (or) dynamic ODT and not enable the Rtt_Nom. For best signal integrity, Rtt_Nom should be set to a low value (RZQ/6 or RZQ/12) and Rtt_WR can be set to either RZQ/4 or RZQ/2. All of these ODT values are part of the DRAM specification

    Gunter Schmer said:

    [] Is dynamic truly mutually exclusive to static ODT, i.e. the static settings in DDR_TERM have no effect, if DYN_ODT is set?

    They are mutually exclusive in the sense that you can enable them independently. However, if you set the DYN_ODT i.e. Rtt_WR to a different value from Rtt_Nom, the ODT value will change for WRITE operation as set in Rtt_WR

    Gunter Schmer said:

    [] The GEL DDR configuration for the SK and IDK are using static ODT RZQ/6 (40 Ohm). How did we arrive at this setting, as it relates to the 2x 16-bit DDR3 device configuration?

    Here is the GEL:

    This one is for GP EVM with 4x 8-bit DDR3 devices

    #define DDR3_SDRAM_CONFIG       0x61A013B2  //32-bit DDR3
               //differential DQS
               //ODT set to RZQ/4; Dynamic ODT set to RZQ/4
               //drive strength = RZQ/6
               //CWL = 5  400MHz
               //CL = 6   400MHz
               //7 = 16 row bits
               //2 = 10 column bits
               //1 chip select

    This one is for SK and IDK with 2x 16-bit DDR3 devices.


    #define IDK_EVM_DDR3_SDRAM_CONFIG     0x61A11B32  //32-bit DDR3
                  //termination = RZQ/6
                  //differential DQS
                  //dynamic ODT off
                  //drive strength = RZQ/6 (lower drive strength for IDK
                  //CWL = 5
                  //CL = 6
                  //7 = 16 row bits
                  //2 = 10 column bits
                  //1 chip select

    The IDK and SK boards have same settings. Basically, Rtt_Nom and Rtt_WR both set to RZQ/4. There is a typo in the comments that might have caused some confusion.

    Regards, Siva