It seems that once the DDR has been enabled through the PSC that it cannot be changed to any other states (e.g. syncreset, etc.). I created a ridiculously simple test case where the ARM simply enables the DDR module through PSC and then attempts to set it to SyncReset. It gets stuck waiting for the GO bit to clear.
The project is attached. Here's the procedure to reproduce the issue:
- Open project in CCS 4 (Project -> Import Existing CCS Project)
- Connect to target (OMAP-L138 EVM, ARM926 core)
- Go to Target -> Advanced Resets -> System Reset (full out reset)
- Target -> Load Program to load the out file
- Set breakpoints on the line after the call to psc1_change_state so you can see the value of ret_val
- You'll see the initial call to put DDR in syncreset succeeds.
- Next call to Enable succeeds.
- When it loops back around and tries to go back to syncreset it fails.
Why is this important? The procedure for enabling the DDR after a power-on reset documented in Section 2.13.2 of the DDR User Guide says to enable the DDR domain in step 2 and then to put it in syncreset in step 5. My simple experiment seems to show this isn't possible for some reason.
(Side note: step 2 actually says just to enable VCLK. I suppose that could be interpreted as changing to syncreset state since that would technically enable the clock, but if that's the case we should avoid using the word "enable" when we want the syncreset case.)
