Hi
I am using TMS320VC5509A processor in SPI slave mode (module 1) and it interface Analog Devices ADSP21368
which is a SPI master. When Master initiates a data transfer by generating data, clock, slave select,
the C5509A slave should generate a interrupt and process the data and acknowledge the same back to master.
When i try the above in polling mode data transfer is fine in both directions. When i want it to be done through ISR, interrupt is not generated. please find the attached code.
//////////////////////main function//////////////////////////////////
#include <csl.h>
#include <csl_chip.h>
#include <csl_std.h>
#include <csl_emif.h>
#include <csl_gpio.h>
#include <csl_irq.h>
#include <csl_mcbsp.h>
#include <csl_pll.h>
#include <csl_rtc.h>
#include <csl_timer.h>
#include <csl_chiphal.h>
#include <csl_rtc.h>
#include "main.h"
extern un_flagreg_t un_flagreg;
interrupt void FPGAInterrupt(void); //
//
interrupt void SPInterrupt(void); // SPI Receive Interrupt
void main(void)
{
int IFRStat;
CSL_init();
ChipInit(); // init system registers and peripherals
// Init McBSP0
// Read FPGA code from second Flash
// config FPGA through McBSP 0
// SelfTest();
// read keys from flash.
// update Bufferkey status, active key status
// if key are active and latch key from active area to FPGA
// FPGA to update the status on LED's.
IRQ_clear(IRQ_EVT_RTC); // clear interrupt
IRQ_clear(IRQ_EVT_INT0); // clear interrupt
IRQ_clear(IRQ_EVT_RINT2); // clear interrupt
// IRQ_setVecs(0xFFFF);
// IRQ_globalDisable();
IRQ_plug (IRQ_EVT_INT0, &FPGAInterrupt); // INTO interrupt from FPGA, this comes only when fillgun is connected for key loading
IRQ_enable(IRQ_EVT_INT0); // Enable INT0 Interrupt
IRQ_plug (IRQ_EVT_RTC, &RTCInterrupt); // RTC interrupt to FPGA for time update
IRQ_enable(IRQ_EVT_RTC); // Enable RTC Interrupt
IRQ_plug (IRQ_EVT_RINT2, &SPInterrupt); // SPI interrupt to CPU for receving TXDR commands
IRQ_enable(IRQ_EVT_RINT2); // Enable SPI Interrupt
IRQ_globalEnable(); // globally enabling of Interrupts by setting INTM bit of ST1 register.
RTC_start();
while(1)
{
}
}
//////////////////////CHIP Initialization////////////////////////
#include <csl.h>
#include <csl_chip.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_gpio.h>
#include <csl_rtc.h>
#include <csl_mcbsp.h>
#include <csl_timhal.h>
#include <csl_pllhal.h>
void ChipInit()
{
Uint16 LockStat;
/* system register initialisation */
CHIP_RSET(SYSR, 0x0000);
asm(" nop; nop; nop; nop; nop; nop; ");
PLL_FSET(CLKMD, PLLENABLE, 1); // PLL enabled
asm(" nop; nop; nop; nop; nop; nop; ");
PLL_FSET(CLKMD, PLLMULT, 9); // ClkIn 12 multipled by 9 to yield 108Mhz
asm(" nop; nop; nop; nop; nop; nop; ");
PLL_FSET(CLKMD, PLLDIV, 0); // Division factor '1'
asm(" nop; nop; nop; nop; nop; nop; ");
// wait till the PLL locks
LockStat =PLL_FGET(CLKMD, LOCK); // read the lock status of PLL
asm(" nop; nop; nop; nop; nop; nop; ");
while (LockStat==0)
{
LockStat =PLL_FGET(CLKMD, LOCK); // wait till the PLL locks
asm(" nop; nop; nop; nop; nop; nop; ");
}
CHIP_RSET(XBSR, 0x0002); // Full EMIF mode.
asm(" nop; nop; nop; nop; nop; nop; ");
CHIP_RSET(IER0, 0x1014); // enable watchdog, Timer0, McBSP RX, External Interrupt
// CHIP_RSET(IER0, 0xFFFF);
asm(" nop; nop; nop; nop; nop; nop; ");
// CHIP_RSET(IER1, 0x0008); // McBSP TX, DMA 0, RTC interrupts.
asm(" nop; nop; nop; nop; nop; nop; ");
/*configure External memory interface FPGA, Flash U1 & U3 */
EMIF_RSET(EGCR, 0x0080); // enable write posting, and ARDY is ON to extend cycles
asm(" nop; nop; nop; nop; nop; nop; ");
// EMIF_RSET(CE03, 0x1FFF); // FPGA ; enable 16 bit ASYC MEM, RDSETUP-15; RDSTROBE-15; RDHOLD-3;
asm(" nop; nop; nop; nop; nop; nop; ");
EMIF_RSET(CE01, 0x1FFF); // Boot Flash U3; enable 16 bit ASYC MEM, RDSETUP-15; RDSTROBE-15; RDHOLD-3;
asm(" nop; nop; nop; nop; nop; nop; ");
EMIF_RSET(CE02, 0x5FFF); // Flash U2 key storage; enable 16 bit ASYC MEM, RDSETUP-15; RDSTROBE-15; RDHOLD-3;
asm(" nop; nop; nop; nop; nop; nop; ");
/*configure GPIO pins */
GPIO_RSET(IODIR, 0x00A0); //
asm(" nop; nop; nop; nop; nop; nop; ");
GPIO_RSET(IODATA, 0xF0); //
asm(" nop; nop; nop; nop; nop; nop; ");
RTC_RSET(RTCINTEN, 0xC2); // configure RTC enable periodoc interrupt, clock mode set 24 hour
asm(" nop; nop; nop; nop; nop; nop; ");
RTC_RSET(RTCPINTR, 0x1F); // RTC Periodic Interrupt every 500ms, so RTC time update to FPGA wil be done every 500ms
asm(" nop; nop; nop; nop; nop; nop; ");
CHIP_RSET(IER1, 0xFFFF);
// Configure MCBSP2 as SPI slave; for guidance on MCBSP refer TI MCBSP guide
MCBSP_FSET(SPCR22,XRST, 0); // place TX and RX in Reset
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,RRST, 0); //
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,DLB, 0); //
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR22,GRST, 0); //Place the sample rate generator in reset.
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,RIOEN, 0); //The DR,FSR,CLKR and CLKS are configured as serial port pins
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,XIOEN, 0); //The DR,FSR,CLKR and CLKS are configured as serial port pins
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,DLB, 0); // The digital loop back mode is disabled.
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,CLKSTP, 3); // The clock stop mode with a clock delay) is selected.
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,CLKXP, 1); // The polarity of CLKX as seen on the CLKX pin is positive
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,CLKRP, 1); // The polarity of CLKR as seen on the CLKR pin is positive
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,CLKXM, 0); //The clock generated by the sample rate generator
asm(" nop; nop; nop; nop; nop; nop; ");
//(CLKG) is derived from the McBSP internal input clock.
MCBSP_FSET(RCR22, RPHASE, 0); //single-phase receive frame
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(XCR22, XPHASE, 0); // single-phase transmit frame
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(RCR12, RFRLEN1, 0); //receive frame length of 1 serial word
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(XCR12, XFRLEN1, 0); //transmit frame length of 1 serial word
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(RCR22, RFIG, 1); //ignores unexpected frame sync pulses
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(RCR22, RCOMPAND, 0); //no companding
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(RCR12, RWDLEN1, 2); //receive frame length of 1 serial word is 16 bits
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(XCR12, XWDLEN1, 2); //transmit frame length of 1 serial word is 16 bits
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,SCLKME,0); // The polarity of CLKR as seen on the CLKR pin is positive
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SRGR22,CLKSM,1);
MCBSP_FSET(SRGR12,CLKGDV, 1); //The sample rate generator divides the McBSP internal
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,FSRM, 1); //receive frame syncronisation is supplied by
asm(" nop; nop; nop; nop; nop; nop; ");//by sample rate generator
MCBSP_FSET(PCR2,FSXM, 0); //
asm(" nop; nop; nop; nop; nop; nop; ");
// MCBSP_FSET(SPCR12,DXENA, 1); // The clock stop mode with a clock delay) is selected.
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(PCR2,FSXP, 1); //
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(RCR22, RDATDLY, 0); //
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(XCR22, XDATDLY, 1); //
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,RINTM, 0); // enable McBSP RX Interrupt
asm(" nop; nop; nop; nop; nop; nop; ");
//input clock by 2 before generating CLKG
MCBSP_FSET(SPCR22,GRST, 1); //Release the sample rate generator from reset.
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR22,XRST, 1); //Enable TX and RX
asm(" nop; nop; nop; nop; nop; nop; ");
MCBSP_FSET(SPCR12,RRST, 1); //
asm(" nop; nop; nop; nop; nop; nop; ");
}
///////////////////////////////////SPI ISR///////////////////////////////////////
#include <csl.h>
#include <csl_chip.h>
#include <csl_mcbsp.h>
#include <csl_irq.h>
#include <csl_std.h>
#include "main.h"
void ACK_TXDR(void);
un_flagreg_t un_flagreg;
Uint16 TXDRControlData;
//Uint16 TXDR_ACKData;
interrupt void SPInterrupt(void)
{
// upon interrupt read receiver data register
// send ack by placing data in transmitter data register
// process controls like Erase, BTA etc.
// Control information
// Emergency Erase: TXDR to slave 0xAAAA; slave to TXDR : 0xBBBB
// Code Zeroize: TXDR to slave 0x5555; slave to TXDR: 0x6666
// BTA: TXDR to Slave 0x3333; slave to TXDR: 0x4444
Uint16 ReceiverReadyFlag=0;
Uint16 ReceiverSyncErr=0;
/*read data if receiver data is ready and is without sync error*/
ReceiverReadyFlag=MCBSP_FGET(SPCR12,RRDY);
ReceiverSyncErr=MCBSP_FGET(SPCR12,RSYNCERR);
if((ReceiverReadyFlag==1)&&(ReceiverSyncErr==0))
{
TXDRControlData=MCBSP_RGET(DRR12); /// format
un_flagreg.st_flagreg.SPIdataflag=1;
ACK_TXDR();
asm(" nop; nop; nop; nop; nop; nop; ");
}
else
{
// read receiver status flags and data again
ReceiverReadyFlag=MCBSP_FGET(SPCR12,RRDY);
ReceiverSyncErr=MCBSP_FGET(SPCR12,RSYNCERR);
if((ReceiverReadyFlag==1)&&(ReceiverSyncErr==0))
{
TXDRControlData=MCBSP_RGET(DRR12);
un_flagreg.st_flagreg.SPIdataflag=1;
ACK_TXDR();
}
else
{
// flag an error;
un_flagreg.st_flagreg.SPIdataflag=0;
}
}
}
/*this function provides acknowledgement for data received on SPI to TXDR */
void ACK_TXDR(void)
{
Uint16 TxReadyFlag=0;
Uint16 TxSyncErr=0;
TxReadyFlag=MCBSP_FGET(SPCR22,XRDY);
TxSyncErr=MCBSP_FGET(SPCR22,XSYNCERR);
// if(TXDRControlData==0x1111) // slave installed
// {
// if((TxReadyFlag==1)&&(TxSyncErr==0)) // check the transmitter is ready
if(TxReadyFlag==1) // check the transmitter is ready
{
MCBSP_RSET(DXR12, 0x4569); // acknowldge with 0x2222
}
// }
if(TXDRControlData==0xAAAA) // emergency erase
{
// if((TxReadyFlag==1)&&(TxSyncErr==0)) // check the transmitter is ready
if(TxReadyFlag==1) // check the transmitter is ready
{
MCBSP_RSET(DXR12, 0xBBBB); // acknowldge with 0xBBBB
un_flagreg.st_flagreg.Emer_Erase=1;
}
}
if (TXDRControlData==0x5555) //code zeroize
{
if(TxReadyFlag==1) // check the transmitter is ready
{
MCBSP_RSET(DXR12, 0x6666); // acknowldge with 0x6666
un_flagreg.st_flagreg.Code_Zeroize=1;
}
}
if (TXDRControlData==0x3333) // BTA
{
if(TxReadyFlag==1) // check the transmitter is ready
{
MCBSP_RSET(DXR12, 0x4444); // acknowldge with 0x4444
un_flagreg.st_flagreg.Buffer_To_Active=1;
}
}
}
