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Reducing Interrupt Latency Using DSP/BIOS in 6713

Alan Neidig
Intellectual 255 points
Other Parts Discussed in Thread: CODECOMPOSER, CCSTUDIO

I need to be able to service an interrupt every 8 microseconds to update 4 values in an external DAC.  The write operation to the DAC takes about 50ns, so that only requires a little over 200ns to complete.  I am having a problem servicing the interrupt at the 8us rate.  It appears to "overload" the BIOS/OS.  I suspect I may have configuration/setup issue.

- Once the 8usec T1 timer tick is enabled, the system seems to be overloaded such that BIOS/OS does not run any other task on the system.
- Although, T1 tick time is set at 8uS, the minimum response is at 12 usecs.
- It seems that T0 (1mS tick) interruption is not executed (preemptive by T1 interruption)
- CECTLx (CS3) register was set to minimized writing cycle (~50nsec)
- Worse case scenario: wave form at 10Khz is generated with 12 DAC values/samples, where the DAC steps are very noticeable.

General Board info:
- board, based on TMS320C6713 DSP @ 150Mhz (CLKIN).
- DAC response time is 8e-6 sec (8uS), 12 bit, 4 channels.
- T1 timer use as the "DAC sample tick"
- T0 used as the BIOS/DSP clock manager
- CodeComposer 4.1.1 (Windows XP SP3)

Questions:
- How the interruption priorities are assigned?
- Can T1 be used at a higher speed tick than T0 when T0 is used as the main clock for BIOS/DSP?
- Can the interruption latencies of the BIOS/DSP be minimized or quantified?

Alan

  • 0
    TI__Mastermind 18130 points

    Alan,

    To answer your specific questions:

    Alan Neidig said:
    - How the interruption priorities are assigned?
    In most (typical) systems the hardware interrupts disable the Global Interrupt Enable (GIE) bit in the Control Status Register (CSR). This means that any interrupt currently being processed is uninterruptible except by Reset/NMI. If two or more interrupts are pending simultaneously then the lowest interrupt number is serviced first (e.g., INT4 would be serviced before INT5).

    Alan Neidig said:
    - Can T1 be used at a higher speed tick than T0 when T0 is used as the main clock for BIOS/DSP?
    Timer1 does not have any dependencies on the BIOS system clock which is Timer0 in your case. As such, if you configure T1 to interrupt at 8uS and the BIOS 'tick' rate is 1ms these should be independent of each other. Keep in mind that an 8us interrupt rate is pretty quick, so there is going to be a lot of context switching into and out of the ISR.

    Alan Neidig said:
    - Can the interruption latencies of the BIOS/DSP be minimized or quantified?
    BIOS HWI module latencies can be found inside the DSP/BIOS installation folder. Depending on where you have installed BIOS the directory may change, but by default these numbers are located in the C:\CCStudio_v3.3\bios_5_31_02\packages\ti\bios\benchmarks\html folder.

    With all that said, you may want to consider offloading these DAC writes from the CPU over to the EDMA module. EDMA operates independent of the CPU, and if you triggered an EDMA transfer off the T1 event this would negate the need for an 8uS interrupt routine. Keeping in mind that the EDMA module is 'stupid' the buffer source would have to be a known address at the time of programming so you can properly configure the EDMA channel, but overall this is probably a 'better' solution for this scenario.