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EDMA CC Using IPR Bit To Indicate Transfer Complete

Chia-Ning Wang
Intellectual 400 points

Hi Ti Engineers,

     I'm running some IPC tests on the C6678 EVM that happen to use EDMA transfers. In this test, I have multiple cores pass a single IPC message in SL2 amongst themselves in a pre-determined order. When the message is received by a core, it will use EDMA transfer to copy data from its input buffer to its output buffer while adding some extra data of its own. The output buffer of the current core will serve as the input buffer of the next core to receive the IPC message. Looking at intermediate as well as final output, it looks like some of the EDMA transfer didn't get to complete before it is copied by the next core. I'm only using one EDMA transfer channel for the test and waiting on the IPR bit for the TC before starting any new transfers. I was therefore wondering if it's because the IPR bit indicates transfer completion when the TC sends the last write command and does not guarantee that the data has arrived at its destination (in this case DDR).

Best Regards,

Johnny

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    I presume that, you are using CSL initialization procedure for EDMA in your example.

    I would suggest first you to check the PaRAM settings before and after you start off the transfer and also check whether the data is wrritten to the corresponding memory location.

    Have you checked the status of interrupt pending register and see whether the corresponding interrupt is pending or not?

    What is your TCC value captured in OPT?

    May be, i could recommend few suggestion below:

    1. Ensure whether TCINTEN bit is enabled in channel OPT and only then, the interrupt pending register (IPR / IPRH) relevant bit position appropriate to the DMA event would be set on transfer completion

    2. Also, please ensure the TCCMODE bit in OPT which would indicate normal or early completion of data transfer. To clarify you that any TCC value cannot be set in the PaRAM and the fact is that the 6-bit TCC would be posted by the TC to the CC after it receives the transfer completion signal from the destination peripheral in normal completion mode. This 6-bit code sets the relevant bit in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupt triggered.

    3. I would suggest you to validate the received TCC code in OPT first and obviously, the corresponding bit position in IPR/IPRH would be set which is directly the TCC value and thereafter, the corresponding IER[TCC] / IERH [TCC] bit would be set to generate a EDMA completion interrupt to the DSP

    Likewise, there are lot many status registers available to you to evaluate the status of interrupts, data transfer completion notification etc. I think, if you could refer the EDMA user guide on the C6678 product folder as below, you could explore more on EDMA interrupt status registers, transfer completion interrupts etc.

    http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

    Usually, EDMA CC would detect a interrupt transfer completion code which is equal to the TCC bit in OPT for the PaRAM entry associated with the DMA channels then the corresponding bit would be set in the interrupt pending register (IPR, IPRH) associated with the channel. For more info. please refer section 4.2.7.4 from the EDMA user guide above.

    Kindly check Appendix A.1 & A.2 for the debug programming tips & check list and check Appendix B.1 for the typical steps & procedure involved in setting up a transfer.

    Thanks & regards,

    Sivaraj K

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