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AM572x warm reset

Tom Newman
Intellectual 380 points

Other Parts Discussed in Thread: AM5728

The Silicon Errata (i862) for the AM5728 states that the porz SoC power-on-reset is the only 100% reliable reset type and provides a recommendation for how this should be implemented.

The Errata also states that other reset sources including the warm reset input (resetn SoC input) can cause the SoC to hang during boot.

Should, therefore, the resetn SoC input be left disconnected?

  • 0
    TI__Guru**** 393215 points
    I suggest you study the AM572x GP EVM schematic (available here: www.ti.com/.../tmdsevm572x and implement a similar circuit.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 380 points

    Biser

    Thanks for your reply.

    That is, in fact, precisely what I am doing but as the Silicon Errata appears to be in conflict with this (and TI's own recommendation is to prioritize the guidance in datasheets over EVM schematics), I was hoping the AM572X team would be able to clarify this. 

    Thanks

    Tom

  • 0 in reply to Tom Newman
    TI__Guru**** 393215 points
    Can you explain what conflict you see?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 380 points

    Hi Biser

    Silicon Errata i862 states "Power-on-reset (porz SoC input signal) is the only 100% reliable reset type. If any reset source other than porz is used, there is a chance the SoC may hang during boot after the reset source is de-asserted. Examples of other reset sources include software resets (global cold, global warm), hardware exception resets (Watchdog, Thermal Shutdown, Security violations), or the Warm Reset input (resetn SoC input). Entry into reset will be successful with these reset sources, but code execution may hang if reset is initiated by any reset source other than porz."

    The GP and Industrial EVM both appear to implement the Warm Reset input (although it would appear there is an unpopulated resistor in the path of the signal in the GP EVM).

    Thanks

    Tom

  • 0 in reply to Tom Newman
    TI__Guru 63605 points
    The JTAG debugger is the only source connected to the RESETN input. When the JTAG debugger asserts reset to RESETN, the AM57xx device will assert RSTOUTN. RSTOUTN is connected the “WARM RESET TO POWER ON RESET TRIGGER” circuit that flows through U9 to the PORZ input which generates the valid PORZ reset.

    Regards,
    Paul
  • 0 in reply to peaves
    Intellectual 380 points
    Paul

    Thanks for clarifying.

    Is there any reason for connecting the JTAG debugger to RESETn rather than having it drive PORZ directly?


    Thanks

    Tom
  • 0 in reply to Tom Newman
    TI__Guru 63605 points
    I checked a pre-production version of the AM572x GP EVM schematic and the JTAG reset source was always connected to RESETN. I suspect JTAG reset was connected to warm reset to be consistent with other TI processors that requires the PMIC to be aware/source a cold reset. However, I don’t see any reason it could not be connected to PORZ for AM572x since the current AM572x GP EVM implementation effectively does the same thing.

    Regards,
    Paul