AM335x HS decoupling capacitors

Larbi Joubala

Other Parts Discussed in Thread: AM3358

I read the am3358 datasheet and i have question on the following chapter 7.7.2.1.2.7 High-Speed Bypass Capacitors. In the table the value "Distance from HS bypass capacitor to device being bypassed" is it available for each decoupling cap of each power pins or just ddr interface power pins? power

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

This table gives guidelines for LPDDR decoupling only. There are separate sections for DDR2 and DDR3. As a general rule HS decoupling capacitors MUST be places as close as possible to the power pins they decouple in order to minimize parasitic inductance. Proper grounding is also important - it's best to use a solid GND plane and place a via to GND as close as possible to the capacitor GND pin.

0 Larbi Joubala over 9 years ago in reply to Biser Gatchev-XID

Prodigy 220 points

Thank you.
But how can i know the max distance where i can put capacitors?

0 Biser Gatchev-XID over 9 years ago in reply to Larbi Joubala

TI__Guru**** 393215 points

There is no such rule. You will have to perform SI analysis if you are not sure that decoupling is placed correctly.

0 Larbi Joubala over 9 years ago in reply to Biser Gatchev-XID

Prodigy 220 points

You mean i need a tool for power integrity analysis? If it is the case which tool do you advise?

0 Biser Gatchev-XID over 9 years ago in reply to Larbi Joubala

TI__Guru**** 393215 points

I can't say. However I don't think you will need PDN analysis if you do a proper power supply layout. There are reference designs you can look at: processors.wiki.ti.com/.../AM335x_Boards and elinux.org/Beagleboard:BeagleBoneBlack

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AM335x HS decoupling capacitors