DRA74xx custom board - unable to get LCD2 clock working

Here is the relevant part of my dts:

fpd_disp1: display@1 {

compatible =  "panel-dpi";

label = "lcd";

  enable-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;

panel-timing {

clock-frequency = <71000000>;

hactive = <1280>;

vactive = <800>;

hfront-porch = <48>;

hback-porch = <80>;

hsync-len = <32>;

vback-porch = <3>;

vfront-porch = <14>;

vsync-len = <6>;

hsync-active = <0>;

vsync-active = <0>;

de-active = <1>;

pixelclk-active = <1>;

};

  port@lcd1 {

  fpd_in1: endpoint {

  remote-endpoint = <&dpi_out1>;

  };

  };

};

&dss {

status = "ok";

vdda_video-supply = <&ldoln_reg>;

  ports {

#address-cells = <1>;

#size-cells = <0>;

            port@lcd {

reg = <0>;

dpi_out: endpoint {

remote-endpoint = <&fpd_in>;

data-lines = <24>;

};

};

port@lcd1 {

reg = <1>;

dpi_out1: endpoint {

remote-endpoint = <&fpd_in1>;

data-lines = <24>;

};

};

};

};

Included dtsi:

4505.dra74x.dtsi.txt

3582.dra7.dtsi.txt

7484.dra7xx-clocks.dtsi.txt

Relevant defconfig:

CONFIG_DRM=y
CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_OMAP=m
CONFIG_DRM_OMAP_NUM_CRTCS=3
CONFIG_DRM_TILCDC=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_OMAP2_DSS=m
# CONFIG_OMAP4_DSS_HDMI_AUDIO is not set
CONFIG_OMAP5_DSS_HDMI=y
# CONFIG_OMAP5_DSS_HDMI_AUDIO is not set
CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
CONFIG_DISPLAY_ENCODER_TPD12S015=m
CONFIG_DISPLAY_DRA7EVM_ENCODER_TPD12S015=m
CONFIG_DISPLAY_SIC_ENCODER_TPD12S521=m
CONFIG_DISPLAY_ENCODER_SII9022=m
CONFIG_DISPLAY_CONNECTOR_HDMI=m
CONFIG_DISPLAY_PANEL_DPI=m
CONFIG_DISPLAY_PANEL_TLC59108=m
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_TI_FPD3_SERDES=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y

Already tried the instructions, without success (that is, image can be seen on Video Out 1 but not on Video Out 2).

Thank you

Hi,

Sorry for the delayed response.

I see that you are trying to run fpd link setup on your LCD2, right? In that case you will need to add a disp_ser dts node & use it with status=enabled.
You can refer to the following link: processors.wiki.ti.com/.../DRA7xx_GLSDK_Software_Developers_Guide

Best Regards,
Yordan

Hi,

Sorry disregard my previous post, the link refers to the dra7xx evm & it has a serializer between the dss pads & display, so unless your setup is similar this won't be very useful.

Best Regards,
Yordan

Hi,
thank you for your reply.

I actually have a fpdlink serializer after the LCD port, but the problem rises before: no valid clock is output by the processor.
I have a serializer also on LCD1 port and there the video output works well.

After digging a bit into the code, I found in drivers/video/fbdev/omap2/dss/dpi.c the following define:

#define HSDIV_PLL 0

It seems that this prevents the driver from setting the correct PLL divider (that has index 2, according to my findings).
From dpi.c:

static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
{
struct dpi_clk_calc_ctx ctx;
int r;
bool ok;

ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
if (!ok)
return -EINVAL;

ctx.pll_params.hsdiv_enabled[HSDIV_PLL] = true; <=== HARDCODED PLL divisor enable

r = pll_set_clock_div(dpi->pll, &ctx.pll_params);
if (r)
return r;

pll_wait_hsdiv_active(dpi->pll, HSDIV_PLL);
dss_select_lcd_clk_source(channel,
dpi_get_alt_clk_src(channel));

dpi->mgr_config.clock_info = ctx.dispc_cinfo;

*fck = ctx.pll_params.clkout_hsdiv[HSDIV_PLL]; <=== HARDCODED PLL divisor enable
*lck_div = ctx.dispc_cinfo.lck_div;
*pck_div = ctx.dispc_cinfo.pck_div;

return 0;
}

Is there a specific reason for this define, that hardcodes the choice of the divider?

Thank you,
Francesco

Hi Francesco,

Francesco Valla said:

Is there a specific reason for this define, that hardcodes the choice of the divider?

 

I am not aware of the reason for hardcoding this to 0. I will try to reach the DSS designers, maybe they could help on this. 

Have you tried tweaking this parameter, does changing this HSDIV_PLL changes the behaviour of your system in any way? 

Best Regards, 
Yordan

Hi,

setting HSDIV_PLL to 2 effectively enables LCD2, but LCD1 does not work anymore.
I will try to expand the driver to dynamically select hsdiv, but if you can check with DSS engineers the reason for the hardcoding that will be helpful.

Thank you

Regards,
Francesco

Hi Praneeth,

I reached quite exactly the same solution just a couple of hours before your post and can confirm that is working on k3.14.

Thank you!

Best regards,
Francesco