I understand that the PMIC for the AM572x is capable of enforcing the power-down sequencing for the AM572x as long as PMIC RESET_IN is driven low at least 1.1ms before the main supply to the PMIC collapses.
In the AM572x GP EVM (sheet 8), it looks as though a supervisory circuit (TPS3808G09) is used to do this. I am, however, unsure as to why this version of the supervisory circuit, which has a 0.9V supply and 0.84V threshold, is used. I note that the minimum input voltage to the PMIC is 3.135V.
Any clarification you are able to provide on this would be much appreciated.
Thanks