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66AK2E05 PCIe

Alok Singh14
Intellectual 350 points

How do you create and translate a 64 bit PCIe inbound window when operating in RC mode?  The Inbound Translation Bar Match Register requires a BAR match value (bits 2-0).  However, when operating in RC mode, the Type 1 Header space within the Keystone II device only contains two BAR registers (BAR0 & BAR1).  BAR0 is reserved for address space 0 and cannot be used.  This does not allow setting up a 64 bit BAR and the Prefetchable Memory Base/Limit must be used.  What BAR match value should be entered in order to translate the incoming PCIe message in this case?

  • 0
    Intellectual 350 points
    Hi,
    Any help will be greatly appreciated..
  • 0
    TI__Guru** 116100 points
    Sorry for the delayed response on this post.
    Will check with internal team for this.
  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru* 95265 points

    Alok,

    For PCIE user guide,

    Section 2.7.2

    Please note that in 64-bit addressing, BAR0 and BAR1 are concatenated and dedicated to Address Space 0. There is no other BAR available in RC mode to map packets with 64-bit addressing to any other internal memory regions with inbound address ranslation.

    Section 2.7.3

    In the case of RC, if the address is in the range configured in the BAR or is outside of the range defined by the three Base/Limit register sets (non-prefetchable memory, prefetchable memory, and I/O), and then that TLP is accepted.

    For an RC port, the use of BAR register is applicable only when the RC port itself has a memory that can be targeted from the PCIe link. The BAR range in the RC is normally must be outside of the three Base/Limit regions.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 350 points

     Eric,

    lding said:

    Section 2.7.3

    In the case of RC, if the address is in the range configured in the BAR or is outside of the range defined by the three Base/Limit register sets (non-prefetchable memory, prefetchable memory, and I/O), and then that TLP is accepted.

    As described in the RC case above, the TLP will be accepted if the address is outside of the range defined by the three Base/Limit register sets.  What happens to the 64 bit PCIe address of the accepted TLP in order to convert it to the internal 32 bit space of the Keystone?

    Regards,

    Alok

  • 0 in reply to Alok Singh14
    TI__Guru* 95265 points
    You need to program the inbound translation registers for the accepted TLP to be routed to 32-bit Keystone memory. Section 2.7.2, you have IB_BAR, HI, LOW, OFFSET to control the mapping.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 350 points

    What value should I put in the BAR register? Can you please provide an example to setup 64 bit  BAR? We are trying to use BAR 0 for Application/Config Space and BAR 1 to provide Address Translation to DDR3 in address space 1.

    Regards,

    Alok

  • 0 in reply to Alok Singh14
    TI__Guru* 95265 points

    BAR0 you can program to 0x21800000, BAR1 leave it to reset default. The incoming is 64-bit address, you need to program IB_BAR, IB_LOW, IB_HI and OFFSET for mapping into DDR3. See the example in PCIE UG example 2-2.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 350 points

    Example 2-2 in PCIE UG only applies to EP not RC. RC only has BAR0 and BAR1. It seems like in 64-bit addressing, BAR0 and BAR1 are concatenated and dedicated to Address Space 0. There is no other BAR available in RC mode to map packets with 64-bit addressing to any other internal memory regions with inbound address translation. Is this true? Can we use BAR2 and BAR2 as well even as RC?

  • 0 in reply to Alok Singh14
    TI__Guru* 95265 points

    You only have BAR0 and BAR1 for RC and BAR0 is used already. I think the incoming packets are accepted by:

    In RC mode, there are another three sets of registers to define the range of rejection.
    • Memory Space (MEM_BASE, MEM_LIMIT)
    • Prefetchable Memory Space (PREFETCH_MEM,PREFETCH_BASE,PREFETCH_LIMIT)
    • IO Space (IO_BASE, IO_LIMIT)

    So, it didn't follow the BAR matching rule. You can try to program IB_BAR to map incoming 64-bit data into DDR by setting IB_BAR0 = 0 or 1 see if it works.

    Regards, Eric