All,
I'm using DDR2: MT47H32M16 (8 Meg x 16 x 4 banks), which is connected to the C6748 mDDR/DDR2 interface.
I have a weird problem -
If a program is linked (all sections) to IRAM, everything works, and I can run memory tests (on the DDR2), access it (using JTAG memory access) etc,
But if some sections are set (in teh project tcf file) to be resided on the DDR2 (sections like .far .bss or other), the program fails to be loaded, and the start-up sequence hangs (usually in specific places, like: hardware reset, cinit00, and others)
Any idea?
My GEL's DDR2 section below
-----------------------------------------
EVICE_mDDRConfig(unsigned int freq)
{
int i;
GEL_TextOut("\tDEVICE_mDDRConfig %d MHz","Output",1,1,1, freq);
/*Enable the Clock to EMIF3A SDRAM*/
PSC1_LPSC_enable(PD0, LPSC_DDR);
#define CLKRZ (0x00002000)
#define LOCK (0x00000080)
#define POWERDN (0x00000040)
#define READY (0x00008000)
#define IOPWRDN (0x00004000)
VTPIO_CTL &= ~( CLKRZ | LOCK | POWERDN ); //a
for (i = 0; i++; i<10) {} // a
VTPIO_CTL |= CLKRZ; // b
while(!((VTPIO_CTL & READY)>>15)) {} // c
VTPIO_CTL |= IOPWRDN; // d
VTPIO_CTL |= LOCK; // e
VTPIO_CTL |= POWERDN; // f
EMIF3A_SDCR |= 0x00800000; // Set BOOTUNLOCK
// **********************************************************************************************
// Setting based on 512Mb DDR MT47H32M16 on DSMP
// Config DDR timings
DDRCTL = (0x0 << 8) | // Reserved
(0x1 << 7) | // EXT_STRBEN
(0x1 << 6) | // PWRDNEN
(0x0 << 3) | // Reserved
(0x3 << 0); // RL
EMIF3A_SDCR = (EMIF3A_SDCR & 0xF0000000) | // Reserved
(0x0 << 27) | // DDR2TERM1
(0x1 << 26) | // IBANK_POS
(0x0 << 25) | // MSDRAMEN
(0x0 << 24) | // DDRDRIVE1
(0x0 << 23) | // BOOTUNLOCK
(0x0 << 22) | // DDR2DDQS
(0x0 << 21) | // DDR2TERM0
(0x1 << 20) | // DDR2EN
(0x0 << 19) | // DDRDLL_DIS
(0x0 << 18) | // DDRDRIVE0
(0x1 << 17) | // DDREN
(0x1 << 16) | // SDRAMEN
(0x1 << 15) | // TIMUNLOCK
(0x1 << 14) | // NM
(0x0 << 12) | // Reserved
(0x3 << 9) | // CL
(0x0 << 7) | // Reserved
(0x2 << 4) | // IBANK
(0x0 << 3) | // Reserved
(0x2 << 0); // PAGESIZE
// Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
EMIF3A_SDTIMR1 = (((unsigned int) ((97.5 * freq / 1000) - 0.5)) << 25) | // tRFC
(((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 22) | // tRP
(((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 19) | // tRCD
(((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 16) | // tWR
(((unsigned int) ((42.0 * freq / 1000) - 0.5)) << 11) | // tRAS
(((unsigned int) ((60.0 * freq / 1000) - 0.5)) << 6) | // tRC
(((unsigned int) ((12.0 * freq / 1000) - 0.5)) << 3) | // tRRD
(EMIF3A_SDTIMR1 & 0x4) | // Reserved
(((unsigned int) ((2.0 * freq / 1000) - 0.5)) << 0); // tWTR
// Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
// tRASMAX is rounded down so subtracting 1
// CAS/CL = 3
EMIF3A_SDTIMR2 = (EMIF3A_SDTIMR2 & 0x80000000) | // Reserved
(((unsigned int) ((70000 * freq / 1000) - 1)) << 27) | // tRASMAX
(0x0 << 25) | // tXP
(0x0 << 23) | // tODT (Not supported)
(((unsigned int) ((120.0 * freq / 1000) - 0.5)) << 16) | // tXSNR
((200 - 1) << 8) | // tXSRD (200 Cycles)
((1 - 1) << 5) | // tRTP (1 Cycle)
(0x0 << 0); // tCKE
EMIF3A_SDCR &= ~0x00008000; // Clear TIMUNLOCK
// EMIF3A_SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply
EMIF3A_SDCR2 = 0x00000004; // 8K rows
EMIF3A_SDRCR = (0x1 << 31) | // LPMODEN
(0x1 << 30) | // MCLKSTOPEN
(0x0 << 24) | // Reserved
(0x0 << 23) | // SR_PD
(0x0 << 16) | // Reserved
/* (((unsigned int) ((7.8 * freq) + 0.5)) << 0); // RR*/
(((unsigned int) ((3.9 * freq) + 0.5)) << 0);
/*SyncReset the Clock to EMIF3A SDRAM*/
PSC1_LPSC_SyncReset(PD0, LPSC_DDR);
/*Enable the Clock to EMIF3A SDRAM*/
PSC1_LPSC_enable(PD0, LPSC_DDR);
EMIF3A_SDRCR &= ~0xC0000000; // disable self-refresh
}
