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Beagle Board cache configuration

Garima
Prodigy 70 points
Other Parts Discussed in Thread: OMAP3530

Hi,

I have one question about cache availability on Beagle board.

We are using Beagle Board B4, running Angstrom linux uImage version 2.6.28.

While we compare the performance of our codecs on Beagle Board with the performance of our codecs on other devices with Cortex-A8 CPU (e.g. iPhone 3GS), there is significant difference in performance (iPhone has much better performance). I suspect that the L1/L2 I/D cache are not enabled on Beagle/Angstrom or full size of cache are not enabled. But i have no way to find out.

I am aware that OMAP3530 has following cache for Cortex-A8:

L1: 32 KB (I+D)

L2: 256 KB (D)

Is there a way that we can see information about cache sizes on beagle board/Angstrom. 

Thanks & regards,

Garima

  • 0
    Intellectual 650 points

    Linux by default ensures that L1 and L2 caches are enabled during boot - i highly doubt that it is disabled, as Linux would not come close in terms of performance if that was the case.

  • 0
    TI__Expert 5960 points

    Hi Garima,

    The Beagle Board B4 has an OMAP3530 chip on it so the cache sizes are the same as you noted.

    Cortex-A8 also has NEON SIMD which is part of the armv7 instruction set.  According to ARM benchmarks, if you utilize NEON, you can expect anywhere from 1.6x to 2.5x speed up on complex video Codecs. For example ARM has built their own H.264 Codec which is based on calls to the OpenMax Libraries  They show a 1.8x speedup using NEON.

    Regards,

  • 0 in reply to JerryJohns
    Prodigy 70 points

    Hi Jerry,

    My doubt is if L1 and L2 cachce on BeagleBoard/Angstrom Linux have been configured to use less than the available L1 and L2 cache on OMAP3530. Is there a way to find out at runtime, how much L1 and L2 cache is available/enabled on BeagleBoard with Angstrom Linux. I am using BeagleBoard B4.

    Regards,

    Garima

  • 0 in reply to Jeff L
    Prodigy 70 points

    Hi Jeff,

    Thanks for your reply.

    I guess that one can configure size of L1 and L2 cache enabled by the kernel, irrespective of how much of it is available on chip.

    For example, OMAP3530 chip has following cache available:

    L1: 32 KB (I+D)

    L2: 256KB (D)

    The Linux kernel might enable use of only part of it, let us say:

    L1: 8 KB (D), 8 KB (I cache)

    L2: 64KB (D)

    Could it be the case?

    Regards

    Garima

    PS. I am already using NEON insructions available on Cortex-A8 for performance.

     

     

  • 0 in reply to Garima
    TI__Expert 5960 points

    Hi Garima,

    I don't think you can change the size of the cache.  There are some internal registers in the ARM to read back your current cache size.

    Looking at the ARM TRM you can select which cache you want to read back using the Cache Size Selection Register (CSSR) using bits [3:1] for level:

    MRC p15, 2, <Rd>, c0, c0, 0 ; Cache Size Selection Register

    For example, if you set the CSSR level to 2, then read back the Current Cache size Selection Register

    MRC p15, 1, <Rd>, c0, c0, 0; Current Cache Size Identification Register

    Table 3-43 Encodings of the Current Cache Size Identification Register

    You should see something like the following for 256K.

     

     

    0xF03FE03A