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EMIFA to FPGA interface clock?

Traian Mitrache
Prodigy 180 points


I can't tell from the data sheet what is EMIFA CLK supposed to be when EMIFA is used in Asynchoronous mode: INPUT or OUTPUT?

EMA_CLK is described as "clock output", but it is only listed as an SDRAM interface specific signal.

Fig 7 / pg25 doesn't even show the EMIFA CLK as one of the signals used, but later timing diagrams (fig 10, 11, etc) use EMA_CLK.

EMA_CLK is mentioned a lot in the SDRAM section, but not talked about at all in the asynchronous section.

 

  • 0
    TI__Guru* 84865 points

    Hi Traian

    EMA_CLK is not used when EMIFA is used in asynchronous mode. EMA_CLK is only relevant for EMIFA SDRAM use case.

    Traian Mitrache said:
    Fig 7 / pg25 doesn't even show the EMIFA CLK as one of the signals used, but later timing diagrams (fig 10, 11, etc) use EMA_CLK.

    The timing diagrams refer to EMA_CLK primarily to refer to EMIFA "module" clock, so that the concept of setup strobe hold timings / cycles can be explained/clarified, as those values are w.r.t to EMIFA module clock

    Side Note: Infact, if needed, you could possibly use the EMA_CLK as a "free running" clock in the system, if you are using EMIFA in async mode , as EMA_CLK pin is individually configurable via the pinmux registers

    Hope this helps.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Prodigy 180 points

    I'm sorry, but you are making this even more confusing. You are saying that the clock is "not used"...But in the description of the Asynchronous Read Operation in Normal Mode (Table 19), the description for the Strobe period clearly explains the use of the CLOCK:

    Strobe period The following actions occur during the strobe period of a read operation:
    1. EMA_OE falls at the start of the strobe period
    2. On the rising edge of the clock which is concurrent with the end of the strobe period:
    · EMA_OE rises
    · The data on the EMA_D bus is sampled by the EMIFA.
    In Figure 10, EMA_WAIT is inactive. If EMA_WAIT is instead activated, the strobe period can be extended by the
    external device to give it more time to provide the data. Section 2.5.7 contains more details on using the
    EMA_WAIT pin.

    The following figures (10, 11, 12) all make references to the EMA_CLK ...

    Is the CLOCK relevant or not? And is this something that the TMS drives to the outside world, or is it being driven by an outside device?

  • 0 in reply to Traian Mitrache
    TI__Guru* 84865 points

    Hi Traian

    I can see how the documentation can be confusing the way it is being described. Really the reference EMA_CLK in timing diagrams for the asynchronous sections should've been replaced by "Internal Clock". We will try to get this fixed in a subsequent revision for the user guide.

    The answer is still, the EMA_CLK signal (IO pin) is not relevant for Asynchronous mode. The reference to clock is really the EMIFA internal module clock that is generated by PLL0_SYSCLK3. The references like "rising edge of the clock" can likely be de-emphasized as the internal clock is a don't care /not-visible from a user perspective.

    Hope this helps?

    Feel free , if you still have doubts on this.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Prodigy 180 points

    So what signal IS present on the EMA_CLK pin, if any ?

    Is there a mirror of the internal clock, that I could use to clock my FPGA?

  • 0 in reply to Traian Mitrache
    TI__Guru* 84865 points

    Yes, it will pass through whatever is the EMIFA module clock source (PLL0_SYSCLK3 or DIV4p5 CLK) to the pin. As I mentioned earlier, in asynchronous mode, you don't need the EMA_CLK pin, so you could technically use it as a free running clock source, for your FPGA .