C6657 EDMA throughput for PCIe

Kzk

Hello,

I'm considering to inhibit a throughput between EDMA and PCIESS. I send data to the outbound buffer of PCIESS by TC0 and TC1. I want to control a detailed management of EDMA transfer from IRAM to PCIESS. Please give me some advice.

1) Can I set RDRATE register of EDMA greater than 4h? I want the read rate to control more slowly.

2) Can I control TeraNet to slow EDMA transfer?

3) How many bytes does the outbound buffer of PCIESS have? Can I adjust the size of it?

Regards,
Kazu

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Kazu,
I will ask our experts to look into this. Thank you for your patience.

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Yes you can change the RDRATE bit RDRATE register but not on the fly, you have to do it while initiation of EDMA3 and it should be static.
We do have latest PCIe example in newer version of Processor SDK which has PCIe + EDMA.
C:\ti\pdk_c665x_2_0_1\packages\MyExampleProjects\PCIE_evmc6657_wSoCFile_C66BiosExampleProject

MCSDK code:
C:\ti\pdk_C6657_1_1_2_6\packages\ti\drv\exampleProjects\PCIE_exampleProject

I think, size of buffer is 164bytes.
#define PCIE_EXAMPLE_DSTBUF_BYTES ((PCIE_BUFSIZE_APP + 1) * PCIE_EXAMPLE_UINT32_SIZE)

0 Kzk over 9 years ago in reply to Titusrathinaraj Stalin

Genius 5785 points

Hello,

I'm afraid, I could ask you same question. RDRATE register in EDMA-UG can't be set greater than 4h. Is this restriction applicable to C6657?

Regards,
Kazu

0 lding over 9 years ago in reply to Kzk

TI__Guru* 95265 points

Yes, this RDRATE (0 ... 4) applies to C6657.

Regards, Eric

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C6657 EDMA throughput for PCIe