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DM3725 dpll2 problem

Dmitry Bodnya
Expert 1140 points

Other Parts Discussed in Thread: DM3725

Hi!

I have a custom board with DM3725 running PSP 04.02.00.07.

During kernel boot I see following message:

clock: disabling unused clocks to save power

clock: dpll2_ck failed transition to bypassed

This happening when kernel sets mpu and iva frequencies to 600 and 520 Mhz(I choose 600 in boot args). And due to my investigation it happens when IVA2 clock state transition is controlled by hardware(CM_CLKSTCTRL_IVA2[1:0] = 3). 

The thing with dpll2 prevents system to reach off/retention state during suspend:

Powerdomain (iva2_pwrdm) didn't enter target state 0

Powerdomain (core_pwrdm) didn't enter target state 0

Powerdomain (per_pwrdm) didn't enter target state 0

But, If I am running my program which uses compression on IVA2, and somewhere inside uses lpm, and after LPM_off is called, it keeps CM_CLKSTCTRL_IVA2[1:0] = 0 

and then during suspend all powerdomains are reaching there states.

My questions are:

1) Does anybody seen such behavior with dpll2 bypass failure?

2) Should dpll2 go to bypass mode when in hardware-supervised mode?

3) What I can do to force dpll2 to normal behavior?

Thanks

  • 0
    Expert 1140 points
    I set up dpll2 frequency in u-boot to 520MHz.
    After that I don't see message about dpll2_ck bypass failure, because IVA already on needed frequency.

    And if I then change OPP:
    echo 300000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
    so it goes ok, inspite of dpll hardware-supervised mode..

    Why during kernel boot dpll2 is failed to go to bypass mode (during dpll reprogram), but when OPP changes it goes to bypass and locks again?
  • 0
    Expert 1140 points
    Ok.

    More clarified now.
    I don't know why dpll2 failed to go to bypass mode during kernel initialization. Even though there is omap3_iva_idle function with such comments:
    /**
    * omap3_iva_idle(): ensure IVA is in idle so it can be put into
    * retention
    *
    * In cases where IVA2 is activated by bootcode, it may prevent
    * full-chip retention or off-mode because it is not idle. This
    * function forces the IVA2 into idle state so it can go
    * into retention/off and thus allow full-chip retention/off.
    *
    **/

    But after I disabled iva2 dpll init in x-loader and u-boot, dpll2 setup become ok during kernel init.
    And after that all powerdomains enters desired state.

    One thing left is that after compression program run lpmOFF code keeps dpll mode not in autoidle state(which is enabled after kernel boot).