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How do I see DSP cache config registers in memory browser?

Matthew Mulvey
Intellectual 300 points

Hello,

From my DSP application code, I am writing to L2WWC (L2 Writeback Word Count Register Section) at address: 01844004h.  But when I look at this region in the memory browser (using CCSv6, and the XDS100v2 debug probe) I don't see this write taking effect.  How can I view the contents of the L1 and L2 configuration registers?   I can't find them in the Registers view in CCS either.

Also, something strange:  here is a line from Table 4-10. (L2 Cache Control Registers) in SPRUFK5A:

0184 4018h - L2IBAR - L2 Invalidate Base Address Register

And here is a line from Table 2-1. (L1P Cache Registers Summary) in the same doc:

0184 4020h L1PIBAR Level 1 Program Invalidate Base Address Register

It looks like overlapping registers.  They are both 32-bit registers, so wouldn't they overlap in memory by 2 bytes?

Thanks for any insights anyone can offer.

- Matt. 

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    I think, you are mistaken. There would be no chances of overlapping of memory between 0x 0184 4018 & 0x 0184 4020 since the address are in hexadecimal,  0x 01844018 is reserved for L2IBAR and 0x 0184 4020 is reserved for L1PIBAR, so, in between, you would have 8 addresses such as 0x 0184 4018, 4019, 401A, 401B, 401C, 401D, 401E, 401F, then how wouldn't they overlap in memory by 2 bytes?

    I think, each 32-bit address would hold 8- bit value which then would require four addresses to hold 32-bit value. Then, there seems to nothing strange and nothing overlapping in memory.

    May be, you shall check all possible cache configurations for C674x devices with 2048K bytes of L2 memory in Figure 2-1 of Section 2.3 in the c674x DSP cache user guide as given below:

    http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf

    Also, please check sections 2.1 & 2.2 for configuring L1 & L2 Caches and also some examples 2-1 & 2-2 in the above doc.

    Please check Section 3 for optimizing the cache performance in the above doc. and you will get a better idea on the same.

    For better understanding on cache usage, cache characteristics and cache optimization, you could refer the C64x+ DSP cache user guide as below, please refer section 2.4.2.2 for maintaining coherence between external memory and cache and there is an example 2-4 for external memory DMA double buffering code, kindly check it

    http://www.ti.com/lit/ug/spru862b/spru862b.pdf

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 300 points
    Oops... I can't believe I made that mistake!
    It is very obvious now that there is no overlap, it was just one of those times where I forgot something very basic.
    Thanks for your response,
    - Matt.