I'm using a Spectrum Digital TCI6482 DSK (mostly identical to the C6455 DSK).
This DSK comes with an example called dsk_app. In this example, EDMA3 is configured to read the AIC23 line input samples provided via MCBSP1. EDMA3 then moves these samples out via MCBSP1 to the AIC23.
The example is configured to transmit 2048 sixteen-bit samples per transfer request.
The example uses the EDMA3 channel events XEVT1 and REVT1 to trigger EDMA3 transfers.
As much as I understand the MCBSP logic, the MCBSP controller asserts XEVT1 to the EDMA3 channel controller whenever a new 16-bit sample can be moved into the MCBSP peripheral. That is, with 48,000 samples per second and stereo signals, this equals to 96,000 XEVT1 events per second.
Similarly, the MCBSP controller asserts REVT1 to the EDMA3 channel controller whenever a new 16-bit sample arrived at the MCBSP peripheral and this sample now is ready to be copied by the EDMA3 controller. This should cause 96,000 REVT1 events per second.
Now my questions:
As the example is configured to DMA-move 2048 samples, does this mean that a single time XEVT1 and REVT1 are asserted, triggering EDMA3 transfers, then 2047 times XEVT1 and REVT1 are needlessly asserted without affecting the currently running EDMA3 transfers?
Compared to the maximum speed of the EDMA3 controller, AIC23's 48000 samples per seconds (Stereo 16-bit, according to my calculations 48,000 samples * 2 stereo channels * 2 byte per channel = 192,000 bytes per second) produce low-bandwidth data. Does the assigned EDMA3 Transfer Controller automatically block while trying to read (or write) data to the MCBSP DRR and DXR registers? Is this EDMA3 Transfer Controller therefore idling most of the time, yet bound to fulfill the rather slow data transmission? If the EDMA3 TC was not blocking, for the receive case it would read identical data; and for the transmit case it would write data out too fast for the MCBSP controller to shift out.
Thanks for any answers, Jerry