Hi all,
I'm hunting a big problem in one of our video applications on a DM642 customized board using CCS 3.0, BIOS 4.90, CGT 5.0 (yes, the project is frozen to this old versions).
We have implemented a software clock, wich is updated by a CLK or PRD handler function every 1ms. The clock is synchronized via network using the SNTP protocol. Everything is fine, the time is very accurate. But under some circumstances the clock time is too slow: using a SNTP sync every 1s I see differences up to 300ms!
My idea is that somebody blocks the interrupts globally or especially the timer 0 interrupt. Tracking down some suspects I found nothing! But one thing I saw: we use the DEV functions, especially in this special test-case very often (dynamic device create/destroy). Removing the DEV functions the time error reduces significantly, nearly 33%. But there is still too much remaining.
My question is: is it possible that there are BIOS functions which may influence the CLK/PRD accurancy? Or are there hardware blocks doing this (on initialization time? Maybe the video port hardware?)
Any ideas? Please tell me!
Kind regards,
Andi