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AM572x PCIe Host set BAR detection

Ilya Afanasiev
Prodigy 210 points
Other Parts Discussed in Thread: AM5728

Hi! I use PCI1_SS1 on EVM AM572X(with am5728) as EP.
How i can detect that the pcie host set the BAR, in order to init IB and OB ATU regions.

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software are you using?
  • 0 in reply to Ilya Afanasiev
    TI__Guru**** 393215 points
    Thanks. I have notified the RTOS team. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    In Processor RTOS SDK, all the BAR, IB/OB are configured locally no matter is PCIE RC or EP. The BAR configuration is done by Pcie_cfgBar() function, which writes into 0x51001010 region. The RTOS software doesn't do the enumeartion process, it relies on both ends to configure itself.

    If you uses other program running on RC side (e.g Linux OS) that does the PCIE enumeration, it will read out the BAR mask of the EP side and assign/write BAR value into the EP side. The RC is also capable of accessing the EP's IB/OB registers and programing them. There is no need for the EP side to detect that host writes into the BAR then program IB/OB registers itself.

    Regards, Eric 

  • 0 in reply to lding
    Prodigy 210 points

    Thank you, it works. I setted match mode BAR to the Atu region params and did't conf BAR by Pcie_cfgBar(). I have a second question. How shall I detect that the RC do MemWr operation to EP memory space, or MemRd from EP memory space?

  • 0 in reply to Ilya Afanasiev
    TI__Guru* 95265 points

    For your second question, the R/W is intitated from the host side, so only host knows, you want to detect there is R/W from EP side? I don't think there is a way for EP to know that. One way is you send an interrupt from host to EP after every R/W, then EP can be notified. 

    Regards, Eric

  • 0 in reply to lding
    Prodigy 210 points

    Sorry for bad question. My board is EP. I don't know when and where host(Linux OS) write data to my(EP) memory space. In pcie EP example, EP wait for full flag in dstBuf[BUF_SIZE], but I think it is do not make effective.

  • 0 in reply to Ilya Afanasiev
    TI__Guru* 95265 points

    Ilya,

    First thing, does Linux host (is it a PC or an embedded system running Linux OS) enumerate AM57x as an PCIE endpoint? If yes, the Linux host is responsible to read the BAR mask of the EP (e.g. the EP request several memory regions from host) and allocate it from host memory. The host can also setup the EP's inbound memory mapping to control where the data lands (EP itself can also do this).

    Then host write data to designated memory on EP side. There is no way for EP to know there is data coming in, unless EP know the location and expecting a new data pattern by monitoring it continously. In our RTOS example, the location is known and we just monitor it. 

    So, for your question "when and where host(Linux OS) write data to my(EP) memory space" ====> where? you need to know this based on the mapping setup. When? either data pattern changes every time, you monitor it; or the host send an interrupt to EP whenever it writes something to EP.

    Regards, Eric