AM572x IO Delay Recalibration

I will forward this to the AM57x team.

Dear Yordan-san,

Thank you for your cooperation.

I have one more question about IO Delay Recalibration.
My customer' IO pad configuration setting is MODESELECT=0b0, DELAYMODE=0b0 (customer uses default IO Timing mode.)
When this condition, does customer should execute IO delay Recalibration sequence after changed AVS voltage for VDD_CORE_L voltage domain?
Please advise me again.

I appreciate your quick reply.

Best regards,
Michi

Hi Michi,

Michi Yama said:

When this condition, does customer should execute IO delay Recalibration sequence after changed AVS voltage for VDD_CORE_L voltage domain?

 

Yes, this is mentioned as a must in the documentation, so we advise that the procedure is followed. 

Best Regards, 
Yordan

Dear Yordan-san,

Thank you for your quick reply.

I have one more question.
Is "IO delay Recalibration sequence" included in any gel files that is provided from TI?
If some gel file includes its sequene, please let me know.

I appreciate your quick reply.

Best regards,
Michi

Dear YOrdan-san,

Thank you for your support.

I have another question regarding the IO Delay Recalibration Sequence.

According to the sequence #6, the pad configuration register must be configured.
First time, it is ok, of course. How about second time, is #6 needed?

For example,
When system is powered on, AVS is not applied yet, and AM5728 power -up with PMIC default voltage.
Then, AVS is enabled, and AVS value of VD_CORE is changed. In this timing, IO delay Recalibration Sequence is needed?
If this case also is needed to execute the recalibration sequence, customer must be modified the code soon, because my
customer already AM5728 system shipped.

Next, after OS booted up, when AVS voltage is changed on the VDD_CORE_L, IO Delay Recalibration Sequence must be
executed again. In this timing, the pad configuration registers already are configured. step#6 must be executed again?

Please advise me.

I appreciate your quick reply.

Best regards,
Michi

Hi,

All GEL files for AM572x devices are public and available with the CCS installation, you could search them for reference to implement this procedure.

I've also contacted the AM572x designers to elaborate. Their feedback will be posted here, when available.

Best Regards,
Yordan

Hi Yama-san,

The AVS voltages should only be set once per boot-up cycle. Additionally, this configuration needs to occur at boot-time. (However, DVFS can still be done when changing OPP after the OS has booted.)  

The basic configuration sequence is to set the AVS voltage and then perform the IO Delay Recalibration Sequence. This configuration would only have to happen once. 

Regards,
Melissa

Dear Melissa-san,

Thank you for your support.

I have more question regarding your information. Because I must explain this to customer.

Please see the below. and give me more information to me.

1) My customer sets AVS voltage (VD_CORE also is changed in this timing) at booting up. But customer does not execute IO Delay Recalibration sequence at this timing. They just set only pad confgulation register. And their system does not have any troubles. How do you think about this? Is IO Delay Recalibration Sequence really needed at Boot time?

2) When IO Delay Recalibration sequence is not execulted at boot time, what issue will be happened? And how is percentage of the issue occurrence?

I appreciate your quick reply.

Best regards,

Michi

Dear Melissa-san,

Thank you for your support.

I have one more question.
The Pad configuration register setting of my customer is 0b0 for Mode select bit. Customer uses only "default IO timing mode".
In this case, is IO Delay Recalibration sequence required when boot time?

I appreciate your quick reply.

Best regards,
Michi
My customer