The question about C6678 MPAX demo

user4489731

Hi,everyone ,

I use C6678EVM and want to use MPAX registers to map the same DDR logical address to different physical address for every core ,the demo's code as following :

#if  1
     lvMarPtr = (volatile uint32_t*)0x08000020;

     H_Value = 0x90000017    ;

     if (coreNum == 0) L_Value = 0x8100003f    ;
     if (coreNum == 1) L_Value = 0x8110003f    ;
     if (coreNum == 2) L_Value = 0x8120003f    ;
     if (coreNum == 3) L_Value = 0x8130003f    ;
     if (coreNum == 4) L_Value = 0x8140003f    ;
     if (coreNum == 5) L_Value = 0x8150003f    ;
     if (coreNum == 6) L_Value = 0x8160003f    ;
     if (coreNum == 7) L_Value = 0x8170003f    ;


     *lvMarPtr++ = L_Value;
     *lvMarPtr++ = H_Value;

     printMPAXOneRegisters(4)  ;

In this demo,core 0.......7 can use the same logical address 0x90000000，and the global address for core1 is 0x91000000，for core2 is 0x92000000......and for core 7 is 0x97000000，the demo is ok.

And now,I want core 0......7 can use the same logical address 0x80000000，and the global address for core1 is 0x81000000，for core2 is 0x82000000......and for core7 is 0x87000000.It is possible ?

How can I change the code ?

Regards,

Simon

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Simon,
We will get back to you shortly on this. Thank you for your patience.

0 Raja over 9 years ago in reply to Raja

TI__Guru* 81335 points

In this demo,core 0.......7 can use the same logical address 0x90000000，and the global address for core1 is 0x91000000，for core2 is 0x92000000......and for core 7 is 0x97000000，the demo is ok.

How are you saying global address for each core is different? Where it is documented?

My understanding is that, each core can not have different global address instead it should have different physical address when the logical address 0x90000000 being accessed from cores. This has been already discussed in your previous threads,

Thank you.

0 user4489731 over 9 years ago in reply to Raja

Intellectual 890 points

Hi,Raja,

Each core have different physical address ,but the physical address is 36-bit,so if I want to look the value in the physical address ,how can I do ?the CCS memory browser only can look the 32-bit address?

And according to the above demo,if core1 changed the value in 0x90000000，the value will be changed in 0x91000000，for core 2 ,changed the value in 0x90000000，and the value will be changed in 0x92000000,and so on .For core 1，if other core changed the value in 0x91000000，the value will be changed in core 1's 0x90000000.so I said 0x91000000，0x92000000.....0x97000000 is global address ,because the other core can use the address to access the core 's DDR private space .Maybe,the value in global address(32-bit) is similar to the physical address (36-bit ),we can use the global address instead ,because we can't look the value in physical address (36-bit )according to CCS.

I think the relationship is similar to everycore's LL2 SRAM(0x00800000) and core n's 0x1n800000.

Do you what I mean？

Thank you

Regards,

Simon

0 Raja over 9 years ago in reply to user4489731

TI__Guru* 81335 points

Simon,

Each core have different physical address ,but the physical address is 36-bit,so if I want to look the value in the physical address ,how can I do ?the CCS memory browser only can look the 32-bit address?

My suggestion:
Please connect to core0 on CCS and read the values on 0x90000000 then disconnect, Connect to core1 on CCS and read the values on 0x90000000 then disconnect and so on.

Thank you.

0 ran35366 over 9 years ago in reply to Raja

TI__Genius 12805 points

I am not sure if I understand the question so please respond back to me:

Indeed CCS can see only logical addresses in the memory browser, but which logical address? It turns out that if you select a core (right click on the core) the logical address corresponds to the physical address that is translated by the same core.

So click on core 0 and look at the logical address 0x9000 0000 and you see physical address 0x8 0000 0000 (or whatever it was configured to in core 0). clock on core 1 and the memory browser of the same address will show you physical address 0x8 1000 0000 (or whatever it was configured to)

You can print the physical memory if you add a line (or lines) like printf("I am core %d and teh value is %d \n", DNUM, *p) where p points at the logical memory

Does it answer your question?

Ran

0 Raja over 9 years ago in reply to ran35366

TI__Guru* 81335 points

Hi Ran,

Exactly, this was my understanding. Thank you so much for the confirmation.

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The question about C6678 MPAX demo