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AM572x VOUT1 clock for McASP

Other Parts Discussed in Thread: AM5728

Hi,

AM5728 TRM section 11.1.2.1 under Notes states that " For synchronization purpose, clkout4 (M7) output of HSDIVIDER is used to source MCASP module and peripheral timers".

1. If VOUT1 clock is used as functional clock for McASP (GFCLK) is it possible to generate all the accurate audio clocks from (for different sampling rates of 48k, 44.1k etc,)?

regards,

Shareef

  • Hi,

    What is your VOUT1 clock frequency?
  • Hi Biser,

    I believe the VOUT1 Clock frequency is 148.5 MHz derived from DPLL_VIDEO1 (with HS DIV set to 1). So my VIDEO1_CLK would be 148.5M /4 going to PRCM as shown in Fig 11-4 of TRM.

    Also I believe this video clock VOUT1 frequency could be one of 27M, 74.25M, 74.25M/1.001, 148.5M and 148.5M/1.001...

    Regards,
    Shareef
  • Hi,

    You should specify, which MCASP interface are you planning to use.. As you can see from Table 24-407. MCASP Clocks and Resets MCASP interfaces do not have the same clocks.
    For example MCASP1 has the following clocks:
    MCASP1_AHCLKR & MCASP1_AHCLKX sourced from either of the bellow clocks:
    - SYS_CLK2
    - XREF_CLK0/1/2/3
    -FUNC_24M_GFCLK
    - ABE_24M_GFCLK
    - ABE_SYS_CLK
    MCASP1_AUX_GFCLK sourced from either of the bellow clocks:
    - HDMI_CLK_DIV
    - VIDEO1/2_CLK_DIV
    - PER_APE_X1_GFCLK_DIV
    IPU_L3_GICLK derived from L3_ICLK <- CORE_CLK <- CORE2_X2_CLK <-DPLL_CORE_CLKOUTX2_H1 <- DPLL_CORE.

    While MCASP2 has the following clocks: MCASP2_AUX_GFCLK, MCASP2_AHCLKR, MCASP2_AHCLKX & L4PER_L3_GICLK.

    I assume, you are talking about MCASPx_AUX_GFCLK (present in all McASPs). The clock frequency may vary depending on the VIDEO CLOCK DIVIDER settings. I suggest you use the Clock Tree Tool (www.ti.com/.../clocktreetool) to verify which settings correspond to different frequencies.

    As for your question "1. If VOUT1 clock is used as functional clock for McASP (GFCLK) is it possible to generate all the accurate audio clocks from (for different sampling rates of 48k, 44.1k etc,)?"

    This is very use case specific, depending on your dpll settings, you might not be able to derive some of the needed audio clocks..

    Best Regards,
    Yordan
  • Hi Yordan,

    I was referring to MCASPx_AUX_GFCLK which is present in all McASPs, I will check about possible audio clock generation from the VOUT1 clocks.

    Also by default in GP EVM of AM5728 PSDK, McASP uses PER_ABE_X1_GFCLK and the same is being derived from the 22.5792MHz crystal? (SYS_CLK2) can you please confirm?

    Regards,
    Shareef
  • Hi, 

    Khader Shareef said:
    Also by default in GP EVM of AM5728 PSDK, McASP uses PER_ABE_X1_GFCLK and the same is being derived from the 22.5792MHz crystal? (SYS_CLK2) can you please confirm?

    Yes, this is correct. As I mentioned you could use the CTT to easily track clock sources & DPLL configurations. 

    Best Regards, 

    Yordan