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AM335x setting priority registers dynamically

shigehiro tsuda
Mastermind 9490 points

Hi,

May the following register of AM335x change setting dynamically?

①System (Transfer Controller) Priority
9.3.1.16 init_priority_0 Register (offset = 608h)
9.3.1.17 init_priority_1 Register (offset = 60Ch)
9.3.1.31 mreqprio_0 Register (offset = 670h)

②LCDC dma priority
13.5.1.16 dma_master_prio bit of LCDDMA_CTRL Register

③EDMA
TC priority
11.4.1.8 QUEPRI Register
DBS
9.3.1.18 tptc_cfg Register (offset = 614h)

④EMIF
7.3.5.15 REG_PR_OLD_COUNT bit field of OCP_CONFIG Register

When those setting dynamically is it in a problem, please tell me which timing those registers should set it in.

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will forward this to the factory experts. Feedback will be posted here when available.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points

    Hi Biser,

    Thank you for quick reply.

    I wait for an answer to the experts of your factory team.

    Because a problem attributable to the high load of internal bus or DDR3 occurs by our customer, I want an answer  as soon as possible.

    Best Regards,

    Shigehiro Tsuda

  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points
    Hi Biser,

    Would there be any additional information from the factory experts?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 393215 points
    No, I am checking what happened with this request.
  • 0 in reply to shigehiro tsuda
    TI__Guru* 85095 points
    Tsuda-san
    When these priority registers were put in the architecture, the expected usage of these registers was that they are typically configured statically , one time upfront in the system. It is not expected to change these registers dynamically through the duty cycle of an application, I have not seen any customers do that and we do not have any empirical data or testing to show the benefits of this.
    I would recommend that they tune these registers statically for their worst case traffic loading and stick with these values.

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Mastermind 9490 points

    Hi Mukul,

    Thank you for your reply.

    I understood that these registers could not set the dynamic only by one setting.

    There is a question by addition.
    Which point in time should the timing of the setting of these registers be?
    1.MLO startup
    2.u-boot startup
    3.OS(linux) startup
    4.At the time of the initialization of the associated driver
    5.Application startup of the associated driver
    6.other

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru* 85095 points
    Hi Tsuda-san
    I discussed this with the software team, and the recommendation is that this one time setting (including EMIF priority) is best done prior to accessing any IPs, therefore it should be done at MLO and not touched by any other software.

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Mastermind 9490 points

    Hi Mukul,

    Thank you for quick reply.

    I understood that MLO start was recommended in the setting timing of these registers.

    As for the timing of the setting of the priority of LCDC and TC, is it right at the initialization of each peripheral?
    By the driver of linux, I seem to do the setting of CM_XXX register enabling the clock supply of each module at the time of driver initialization.

    Please tell me the point of the determination of value method of the setting of the register of these priority.

    Best Regards,

    Shigeiro tsuda

  • 0 in reply to Mukul Bhatnagar
    Mastermind 9490 points
    Hi Mukul,

    Is there any update information ?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to Mukul Bhatnagar
    Mastermind 9490 points

    Hi Mukul,

    Thank you for your support.

    Is not the problem in the following understanding?

    1.Register to set in MLO
    ・System (Transfer Controller) Priority
    9.3.1.16 init_priority_0 Register (offset = 608h)
    9.3.1.17 init_priority_1 Register (offset = 60Ch)
    9.3.1.31 mreqprio_0 Register (offset = 670h)

    ・DDR
    7.3.5.15 REG_PR_OLD_COUNT bit field of OCP_CONFIG Register

    2.Register to set by the initialization of the driver
    ・LCDC dma priority
    13.5.1.16 dma_master_prio bit of LCDDMA_CTRL Register

    ・EDMA
    TC priority
    11.4.1.8 QUEPRI Register
    DBS
    9.3.1.18 tptc_cfg Register (offset = 614h)

    When we change it dynamically, what kind of problem will occur?
    Is AM335x hung up?
    Our customer says that they want to decide the determination of value while setting it again after application worked.

    Best Regards,

    Shigehiro Tsuda