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DM8168: How to map 256Mb DDR3 as one continious area?



Hello.

I have custom board with dm8168 rev 2.1 and 2 ddr3 chips mt41j64m16 128 MB connected to emif0 without interleaving.
I use u-boot from EZSDK 5_05_02_00. DDR3 is successfully initialized and I can see memory and read/write. Checked with CCS studio memory browser and mw.b cmd in u-boot.

I want to map these 256 MB as one continious memory area, BUT I noticed that every 16 MB first 4 KB are mirroring the contents of next 4 KB.

0x80000000 - ddr3 start addr
0x80000000 - 0x80000fff - data 1
0x80001000 - 0x80001fff - data 2
...
0x81000000 - 0x81000fff - data 3
0x81001000 - 0x81001fff - data 4
...

data 1 and data 2 are mirroring each other: if I change memory value at 0x8000 0004 the value at 0x80001004 will be same as at 0x8000 0004 and vice versa.
Same situation for 0x8100 0000 area and 0x8200000 etc. data3 reflects data4. Could you people tell me why is this happening?

I disabled emif1 in u-boot code and edited LISA registers. Here's the code I have in evm.c sdram init function:

__raw_writel(0x2, CM_DEFAULT_DMM_CLKCTRL);            
while((__raw_readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2);        /*Poll for Module is functional*/

#ifdef CONFIG_MINIMAL
    /* Program the DMM for non-interleave setting */
    __raw_writel(0x80400100, DMM_LISA_MAP__0);
    __raw_writel(0x0, DMM_LISA_MAP__1);
    __raw_writel(0x0, DMM_LISA_MAP__2);
    __raw_writel(0x0, DMM_LISA_MAP__3);
#else

    /*Enable Tiled Access*/
    __raw_writel(0x80000000, DMM_PAT_BASE_ADDR);

emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF & 0xFFFFFFF, EMIF_SDCFG, EMIF_PHYCFG);

I use minimal config with several modifications: enabled ethernet.

These 4 LISA registers confused me a bit. Is it correct that 0 and 1 LISA MAP are emif0 CS[0] and CS[1] related and 2/3 are emif1 CS[0] CS[1] ?

My assumption is that I have to tune DMM and PAT. But TRM says that PAT uses direct access mode by default. I plan to load linux into DDR later, but I need to transfer big chunk of data through DDR using u-boot before loading OS. That's why I need one continious area. Could anyone tell me what I am doing wrong and give me some clue?

  • Hi Andrei,

    See if the below patch will be in help:

    processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boo#FAQ

    BR
    Pavel
  • Pavel, thanks for reply.
    I disabled emif1 and use only emif0. I also checked lisa_map.

    I realised that entire memory is divided by 4kb areas and these areas are mirroring each other. And changing LISA regs only affects the base system address. I tested it with code composer studio:

    0x80004000 - 0x80004FFF - data1
    0x80005000 - 0x80005FFF - data2
    data1 and data2 is reflecting each other.

    0x80006000 - 0x80006FFF - data3
    0x80007000 - 0x80007FFF - data4
    same for data3 and data4.

    0x80008000 - 0x80008fff - data5
    0x80009000 - 0x80009fff - data6
    data5 and data6 is reflecting.

    etc.

    I'm stuck. How to disable PAT and TILER at all? I just need to map memory as continious area. Could anyone tell me how to tune PAT/TILER correctly?
  • Andrei,

    I made one test on the DM816x TI EVM, which come with 1GByte DDR3, 512MB on EMIF0 and 512MB on EMIF1.

    I am using the latest version of the u-boot code base:

    arago-project.org/.../

    And I have the below:

    U-Boot 2010.06 (Aug 11 2015 - 14:32:51)

    TI8168-GP rev 1.1

    ARM clk: 987MHz

    DDR clk: 796MHz

    I2C:   ready

    DRAM:  1 GiB

    DCACHE:  Off

    ...

    TI8168_EVM#md.l 0x80000004 1

    80000004: 354b9aca    ..K5

    TI8168_EVM#md.l 0x80001004 1

    80001004: 61d1bbdb    ...a

    TI8168_EVM#mw.l 0x80000004 0x6

    TI8168_EVM#md.l 0x80000004 1

    80000004: 00000006    ....

    TI8168_EVM#md.l 0x80001004 1

    80001004: 61d1bbdb    ...a

     

    As you can see from the log, the value in 0x80000004 (0x6) do not mirror with 0x80001004.

    Can you try with the latest u-boot code base, adjusted with your custom board (256MB on EMIF0 only)?

    Note also that the issue might be caused by improper schematic design of the DDR3 address lines.

    See also the below wiki page:

    Regards,
    Pavel

  • Pavel, thx for tip. I've downloaded new u-boot from arago rep and compared ddr init code. I set wrong pagesize in SDRCR register. Now ddr seems to be working fine.

    Topic closed.