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MACSTATUS IDLE bit question

g_dejesus
Prodigy 60 points


I'm running a C6455 (with MACSEL configured for GMII) on a custom board .  I can't get the TI DSP to talk to the PHY.  Looking at the MACSTATUS register, IDLE (bit 31) is 0.  In the EMAC/MDIO documentation (spru975b pp115) it states:  

"EMAC idle bit. This bit is set to 0 at reset; one clock after reset it goes to 1.

    0 The EMAC is not idle
    1 The EMAC is in the idle state"

Which clock is this referring to?

  • 0
    TI__Expert 6815 points

    Just by looking at the user guide, since you are refering to a MAC register with EMAC in GMII mode, the clock generated by the EMAC is GMTCLK. So I assume the doc refers to the GMTCLK (Hope someone more knowledgable corrects me if I'm wrong).

    I found the following description relating GMTCLK to the SYSCLK1 PLL on Page 14 of the spru975b,  "The SYSCLK1 of the secondary PLL controller sources the GMTCLK. The divider generating SYSCLK1 needs to be programmed to /2 (the default value) for this interface to provide a 125 MHz clock to the EMAC."

  • 0 in reply to Aditya
    TI__Expert 6815 points

    Hi,

     

    Was your query answered? Can you mark this as verified if you found what you were looking for? Thanks.