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SRIO PLL output frequency for 66AK2H12

UNA
Mastermind 7980 points
Other Parts Discussed in Thread: 66AK2H12
Hello,
 
I have a question about SRIO PLL output frequency of 66AK2H12.
 
Our custom board is used 156.25Mhz ref clock for SRIO I/F of 66AK2H12.
I have set the Line Rate to 5Gbps by using following Processor SDK.
 
・Processor SDK for 66AK2HX Processors - Linux and TI-RTOS support
http://www.ti.com/tool/PROCESSOR-SDK-K2H
 
The PLL output frequency is described in  Hardware Design Guide for KeyStone II Devices(SPRABV0) as follows :
  
I did not know PLL multiplier setting in your documents for SRIO of Keystone2, but I think that Rate Scale Value is set to 0.25(Full),
because the LANExCTL_STS.TX0_RATE_VAL has set to 0(Full rate mode) by the SDK.
 
   line rate Mbps = PLL Output / rate scale
      ==>  5000 Mbps = PLL Output / 0.25,  PLL Output is 1250 Mhz
 
However, The document(SPRABV0) is described that the PLL output frequency must fall within this range(1562.5Mhz to 3125Mhz).
So, I think that the the setting by the SDK does not meet.
Is my thinking correct?
 
Best regards,
H.U 
  • 0
    TI__Guru* 81335 points

    Hi H.U,

    Yes. Your thinking should be correct. Even I am not sure, why Table 17 SRIO PLL Multiplier Settings of Hardware Design Guide(SPRABV0) does not have full rate scale(0.25) settings.

    We will get back to you on this. Thank you for your patience.

  • 0 in reply to Raja
    TI__Mastermind 46460 points

    H.U,

    The text that you copied from the Hardware Design Guide for KeyStone II devices appears to have been copied verbatim from the Hardware Design Guide for KeyStone I devices.  KS-I and KS-II have different SERDES modules.  The SERDES PLLs are part of the SERDES blocks.  Therefore, the text that you identified is not directly applicable.  Please refer to the KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide (SPRUHO3A) at: www.ti.com/lit/pdf/spruho3.  This described the SERDES registers for the scale settings in the CDR.  The configurations implemented are provided by the silicon vendor that created the SERDES blocks.  These have been fully tested.  You do need to verify that you are using the latest version of ProcessorSDK to be sure that you have the correct configuration.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points
    We will start the process to have the KS-II HDG updated.
    Tom
  • 0 in reply to Tom Johnson 16214
    Mastermind 7980 points
    Hi, Tom

    Thank you for your reply.
    I understand, I hope that the KS-II HDG is update ASAP.

    Best regards,
    H.U