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AM335x DDR3 tDQSCK questions

Yasunori Saito
Intellectual 460 points

Hi,

I have a question about AM335x DDR3 I/F and tDQSCK(JEDEC DDR3 Spec).

I refer to Table 7-58 in AM335x Data Manual(sprs717j).
For 400MHz DDR3 clock frequency, the minimum requirement is DDR3-1600.

I also refer to Table 68 in JEDEC DDR3 Specification(JESD79-3F).
In DDR3-1600 Timing Parameters, tDQSCK is defined as +/-225ps.

Additionaly, DDR PHY register values(XXXX_SLAVE_RATIO) are determined using Software Leveling, because Hardware Leveling is not supported in AM335x DDR3 I/F.

Q1.
RD_DQS_SLAVE_RATIO is the delay value for Read DQS.
Therefore, I think that DATA_PHY_RD_DQS_SLAVE_RATIO.RANGE in Software Leveling Results is important to adapt tDQSCK.
To adapt tDQSCK min/max, I think that DATA_PHY_RD_DQS_SLAVE_RATIO.RANGE must show the time that is longer than tDQSCK*2(min to max). If it is shorter than tDQSCK*2, I think that the read failures may occur.

As examples,
For DDR_CK=400MHz, unit time of ratio value is 9.765625ps(=1/400MHz/256).
For DDR3-1600 memory, required time for tDQSCK is 450ps(=225ps*2).
450 / 9.765625 = 46.08
For DDR3-1600.tDQSCK, RD_DQS_SLAVE_RATIO.RANGE must be more than 47(0x2F).

Is this correct?
If the above is incorrect, Please tell me how to adapt tDQSCK.

Best Regards,
Yasunori

  • 0
    TI__Guru**** 393215 points
    Hi,

    For AM335x there are established DDR3 design procedures. The DDR3 interface should be designed by following section 7.7.2.3 from the AM335x Datasheet Rev. J. DDR3 configuration should be done by following these guides:
    processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
    processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

    The second wiki guide outlines all necessary steps for successful DDR3 software leveling procedure.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Hi Biser,

    Thank you for your reply.

    I am already checking those information.
    But, that is not what I want to know.

    Does AM335x adapt tDQSCK if designed according to guidelines?

    I think as follows.

    tDQSCK is the difference between CK,CK# and DQ,DQS#.
    RD_DQS(memory output) may move in the allowed range between tDQSCK.min and tDQSCK.max.

    DDR3 Controller has to read the data correctly in the range between tDQSCK.min and tDQSCK.max.
    It means that the readable range must be more than the difference between tDQSCK.min and tDQSCK.max.

    RD_DQS_SLAVE_RATIO in AM335x DDR PHY Settings is the delay value for RD_DQS.
    In AM335x Software Leveling Results,
    DATA_PHY_RD_DQS_SLAVE_RATIO.MIN is the minimum value that succeeded in the read access.
    DATA_PHY_RD_DQS_SLAVE_RATIO.MAX is the maximum value that succeeded in the read access.
    Therefore, DATA_PHY_RD_DQS_SLAVE_RATIO.RANGE is the range that succeeded in the read access.

    So, the DATA_PHY_RD_DQS_SLAVE_RATIO.RANGE time must be more than the difference between tDQSCK.min and tDQSCK.max.
    When RD_DQS(memory output) is outside on the range that succeeded in the read access, AM335x DDR I/F will fail in the read access.

    Is this correct, or not?

    Best Regards,
    Yasunori

  • 0 in reply to Yasunori Saito
    TI__Genius 9625 points
    Yasunori-san

    tDQSCK is the delay between the rising edge of CLK to the rising edge of DQS where as the objective of Read leveling is to center the Read DQS in the valid Read Data eye. Therefore, the RD_DQS range has no relationship with the tDQSCK range.

    Regards, Siva
  • 0 in reply to sivak
    Intellectual 460 points

    Hi Siva-san,

    Thank you for your help.

    I understood the RD_DQS range has no relationship with the tDQSCK range.
    I have additional questions.

    Can the AM335x DDR3 Controller adapt the tDQSCK range?
    And, How can I judge it?

    I don't know the way to ensure that the AM335x DDR3 controller can adapt the tDQSCK range.
    Also, the way to confirm it.
    Please tell me.

    Best Regards,
    Yasunori