To whom it may concern - Hello
I would like to ask you to advise about optimizing the NAND Flash read access-time of the DaVinci processor.
We need this optimization at boot time.
The NAND device is connected to CS0.
Please see below what we have come up with until now:
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According to the Logic Analyzer, our read cycle time in Read Page mode is about 550nS.
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Originally, the CSRDOFFTIME parameter in GPMC_CONFIG2 _0 register was 8, which resulted in 80nS CS time.
Reducing this parameter to 3 resulted in 30nS CS time, which implies that the internal GPMC clock cycle time is 10nS (100MHz). -
PAGEBURSTACCESSTIME parameter in GPMC_CONFIG5_0 register is set to 0 (minimum interval between successive reads)
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RDCYCLETIME parameter in GPMC_CONFIG5_0 register was originally set to 10.
Reducing this parameter to 5 had no effect on the intervals between readings, which remained 550nS.
Please advise how can we reduce the reading cycle time.
The other strategy I would like to ask you to examine is using the Pre-fetch and Write-Posting Engine (Reference Manual, pages 1687, 1693, 1698).
Thanks –
