AM572x DDR3 issue - U-boot fails

Wolfram Stumpf

Intellectual 445 points

Other Parts Discussed in Thread: AM5728

Hi there,

I'm currently working on the first-time operation of our AM5728 SR2.0 based board. I have two banks:

EMIF1 with 1GB (2 x Micron MT41K256M16) with ECC (1 x Micron MT41K256M16) and
EMIF2 with 1GB (2 x Micron MT41K256M16) w/o ECC

I can access the A15 via XDS100v2 USB debug probe.
I did use the SPRAC36_EMIF_RegisterConfig_v2 tool to get the proper register values for our DDR3 chips & board.
I updated the GEL scripts for the AM5728 EVM with the values from the XLS + some adaptations for the two banks w/o interleaving
et voila: I can access both banks at 0x80000000 (EMIF1) and 0xC0000000 (EMIF2)

Next step was uboot:

I generated a new board below vendor=TI to have the common stuff easy
I did some initial mods to adapt to our board
I (tried to) updated the VTT enable stuff, memory config (emif_get_reg_dump, emif_get_reg_dump, emif_get_reg_dump, values from the XLS, ...) and DMM setup in board.c
I got the #RESET board ... stuff on the RS232, but trouble on the DDR3

First issue: I got no clock. At first glance, I found that the memory is put in self refresh in emif_update_timings(...) in emif-common.c. For the quick win, I simply commented out the &emif->emif_pwr_mgmt_ctrl stuff.

After that, I can "access" both memories, but the memory content is not stable.

Question:

Is there an updated uboot for the SR2.0 of AM5728?
Is there probably something special in uboot regarding SR2.0 and DDR3?
It looks a bit like the hw calibration is not used or disabled or so. Any hints in that direction?

Maybe there is some knowledge arround to help me get on track. As the GEL settings seem to work quite good, I feel so close to being able to continue with uboot in DDR3 ...

Kind regards

Wolfram Stumpf

over 10 years ago

0 Yordan Kovachev over 10 years ago

TI__Guru**** 161600 points

Hi,

Wolfram Stumpf16 said:
Is there an updated uboot for the SR2.0 of AM5728?

The latest u-boot is u-boot-2015.07 from SDK02.00.02.11. You can download the sources from here: http://www.ti.com/tool/PROCESSOR-SDK-AM57X

Wolfram Stumpf16 said:
Is there probably something special in uboot regarding SR2.0 and DDR3?

There are some IO delay configurations on some of the device pads, you could check arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c file.

The EMIF/DDR settings for AM572x GP evm can be found in board/ti/am57xx/board.c, also check arch/arm/cpu/armv7/omap5/emif.c & arch/arm/cpu/armv7/omap5/sdram.c

Wolfram Stumpf16 said:
It looks a bit like the hw calibration is not used or disabled or so. Any hints in that direction?

Do you mean leveling? If so, then have in mind the following TRM NOTE: "Software leveling is not recommended to be used. Hardware leveling must be used instead."

Could you share what values are you writing to the EMIF registers? I usually recommend to customers to refer to AM572x DDR GEL files.

Best Regards,
Yordan

0 Wolfram Stumpf over 10 years ago in reply to Yordan Kovachev

Intellectual 445 points

Hi,

U-boot-2015.07 from SDK02.00.02.11 was my starting point. I also took in the pin mux data & iodelays from the PinMux-Tool. Besides that, I saw that there are not special settings for the DDR pins in the iodelay data from PinMux.

Regarding the levelling, I was wondering whether the SDK-uboot enables HW levelling or not.I'm not heading towards SW levelling.

Find below my configuration.

Going through your hints, I did a memory dump of the EMIF registers for the GEL and uboot setup. I found, that EMIF*_EXT_PHY_CTRL_26-35 left at 0x00000000 for the GEL. For uboot, I used the values calculated by the Excel for uboot. If I clear 26-35 to 0x0, my DDR3 works.

Question: Why that? Does the EMIF XLS need an update?

Furthermore, I wonder wheter it is safe to comment out the code in emif-common.c:

 	if (omap_revision() == OMAP4430_ES1_0) {
	/* ES1 bug EMIF should be in force idle during freq_update */
 		writel(0, &emif->emif_pwr_mgmt_ctrl);
 	} else {
 		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 	}

It seems to place the DDR3 in self refresh at the end. I wonder, how the full uboot can be loaded to RAM with this code active?

static const struct dmm_lisa_map_regs AM572x_DDR3L_532MHz_HYDRA_dmm_regs = {
    .dmm_lisa_map_0 = 0x80600100,
    .dmm_lisa_map_1 = 0xC0600200,
    .dmm_lisa_map_2 = 0x00000000,
    .dmm_lisa_map_3 = 0x00000000,
    .is_ma_present = 0x1
};

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
	*dmm_lisa_regs = &AM572x_DDR3L_532MHz_HYDRA_dmm_regs;
}

static const struct emif_regs AM572x_DDR3L_532MHz_HYDRA_emif_regs = {
    .sdram_config_init = 0x61851B32,
    .sdram_config = 0x61851B32,
    .sdram_config2 = 0x00000000,
    .ref_ctrl = 0x000040F1,
    .ref_ctrl_final = 0x0000081A,
    .sdram_tim1 = 0xCEEF2673,
    .sdram_tim2 = 0x308F7FDA,
    .sdram_tim3 = 0x407F88A8,
    .read_idle_ctrl = 0x00050000,
    .zq_config = 0x5007190B,
    .temp_alert_config = 0x00000000,
    .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
    .emif_rd_wr_lvl_ctl = 0x00000000,
    .emif_ddr_phy_ctlr_1_init = 0x0024400B,
    .emif_ddr_phy_ctlr_1 = 0x0E24400B,
    .emif_rd_wr_exec_thresh = 0x00000305
};

static const u32 AM572x_DDR3L_532MHz_HYDRA_emif1_ext_phy_regs [] = {
    0x04040100,        // EMIF1_EXT_PHY_CTRL_1
    0x006B0527,        // EMIF1_EXT_PHY_CTRL_2
    0x006B0531,        // EMIF1_EXT_PHY_CTRL_3
    0x006B04F4,        // EMIF1_EXT_PHY_CTRL_4
    0x006B04E0,        // EMIF1_EXT_PHY_CTRL_5
    0x006B04A8,        // EMIF1_EXT_PHY_CTRL_6
    0x00320032,        // EMIF1_EXT_PHY_CTRL_7
    0x00320032,        // EMIF1_EXT_PHY_CTRL_8
    0x00320032,        // EMIF1_EXT_PHY_CTRL_9
    0x00320032,        // EMIF1_EXT_PHY_CTRL_10
    0x00320032,        // EMIF1_EXT_PHY_CTRL_11
    0x00600137,        // EMIF1_EXT_PHY_CTRL_12
    0x0060012D,        // EMIF1_EXT_PHY_CTRL_13
    0x0060016B,        // EMIF1_EXT_PHY_CTRL_14
    0x0060017F,        // EMIF1_EXT_PHY_CTRL_15
    0x006001B6,        // EMIF1_EXT_PHY_CTRL_16
    0x00400117,        // EMIF1_EXT_PHY_CTRL_17
    0x0040010D,        // EMIF1_EXT_PHY_CTRL_18
    0x0040014B,        // EMIF1_EXT_PHY_CTRL_19
    0x0040015F,        // EMIF1_EXT_PHY_CTRL_20
    0x00400196,        // EMIF1_EXT_PHY_CTRL_21
    0x00800080,        // EMIF1_EXT_PHY_CTRL_22
    0x00800080,        // EMIF1_EXT_PHY_CTRL_23
    0x40010080,        // EMIF1_EXT_PHY_CTRL_24
    0x08102040,        // EMIF1_EXT_PHY_CTRL_25
    0x005B0517,        // EMIF1_EXT_PHY_CTRL_26
    0x005B0521,        // EMIF1_EXT_PHY_CTRL_27
    0x005B04E4,        // EMIF1_EXT_PHY_CTRL_28
    0x005B04D0,        // EMIF1_EXT_PHY_CTRL_29
    0x005B0498,        // EMIF1_EXT_PHY_CTRL_30
    0x00300107,        // EMIF1_EXT_PHY_CTRL_31
    0x003000FD,        // EMIF1_EXT_PHY_CTRL_32
    0x0030013B,        // EMIF1_EXT_PHY_CTRL_33
    0x0030014F,        // EMIF1_EXT_PHY_CTRL_34
    0x00300186,        // EMIF1_EXT_PHY_CTRL_35
    0x00000077        // EMIF1_EXT_PHY_CTRL_36
};

static const u32 AM572x_DDR3L_532MHz_HYDRA_emif2_ext_phy_regs [] = {
    0x04040100,        // EMIF2_EXT_PHY_CTRL_1
    0x006B03CC,        // EMIF2_EXT_PHY_CTRL_2
    0x006B03B8,        // EMIF2_EXT_PHY_CTRL_3
    0x006B045E,        // EMIF2_EXT_PHY_CTRL_4
    0x006B03CC,        // EMIF2_EXT_PHY_CTRL_5
    0x006B006B,        // EMIF2_EXT_PHY_CTRL_6
    0x00320032,        // EMIF2_EXT_PHY_CTRL_7
    0x00320032,        // EMIF2_EXT_PHY_CTRL_8
    0x00320032,        // EMIF2_EXT_PHY_CTRL_9
    0x00320032,        // EMIF2_EXT_PHY_CTRL_10
    0x00320032,        // EMIF2_EXT_PHY_CTRL_11
    0x006001F1,        // EMIF2_EXT_PHY_CTRL_12
    0x00600205,        // EMIF2_EXT_PHY_CTRL_13
    0x0060015F,        // EMIF2_EXT_PHY_CTRL_14
    0x006001F1,        // EMIF2_EXT_PHY_CTRL_15
    0x00600060,        // EMIF2_EXT_PHY_CTRL_16
    0x004001D1,        // EMIF2_EXT_PHY_CTRL_17
    0x004001E5,        // EMIF2_EXT_PHY_CTRL_18
    0x0040013F,        // EMIF2_EXT_PHY_CTRL_19
    0x004001D1,        // EMIF2_EXT_PHY_CTRL_20
    0x00400040,        // EMIF2_EXT_PHY_CTRL_21
    0x00800080,        // EMIF2_EXT_PHY_CTRL_22
    0x00800080,        // EMIF2_EXT_PHY_CTRL_23
    0x40010080,        // EMIF2_EXT_PHY_CTRL_24
    0x08102040,        // EMIF2_EXT_PHY_CTRL_25
    0x005B03BC,        // EMIF2_EXT_PHY_CTRL_26
    0x005B03A8,        // EMIF2_EXT_PHY_CTRL_27
    0x005B044E,        // EMIF2_EXT_PHY_CTRL_28
    0x005B03BC,        // EMIF2_EXT_PHY_CTRL_29
    0x005B005B,        // EMIF2_EXT_PHY_CTRL_30
    0x003001C1,        // EMIF2_EXT_PHY_CTRL_31
    0x003001D5,        // EMIF2_EXT_PHY_CTRL_32
    0x0030012F,        // EMIF2_EXT_PHY_CTRL_33
    0x003001C1,        // EMIF2_EXT_PHY_CTRL_34
    0x00300030,        // EMIF2_EXT_PHY_CTRL_35
    0x00000077        // EMIF2_EXT_PHY_CTRL_36
};

void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
	switch (emif_nr) {
	case 1:
		*regs = &AM572x_DDR3L_532MHz_HYDRA_emif_regs;
		break;
	case 2:
		*regs = &AM572x_DDR3L_532MHz_HYDRA_emif_regs;
		break;
	}
}

void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
	switch (emif_nr) {
	case 1:
		*regs = AM572x_DDR3L_532MHz_HYDRA_emif1_ext_phy_regs;
		*size = ARRAY_SIZE(AM572x_DDR3L_532MHz_HYDRA_emif1_ext_phy_regs);
		break;
	case 2:
		*regs = AM572x_DDR3L_532MHz_HYDRA_emif2_ext_phy_regs;
		*size = ARRAY_SIZE(AM572x_DDR3L_532MHz_HYDRA_emif2_ext_phy_regs);
		break;
	}
}

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AM572x DDR3 issue - U-boot fails