the questions about entry address

Hi,Raja,

    As you said ,I have added the delay function and the code as following :

	if(DNUM==0)
	{
		for (core = 1; core < 8; core++)
		{
			if(DEVICE_REG32_R(BOOT_MAGIC_ADDR(core))==0)
			{
	    DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)&_c_int00);
		
			}
		}
		platform_delay(1000);
	}

        and core 7 can't connect CCS:

Regards,

Simon

Hi,Titus,

         Yes,I have modified the code ,the code without modifying can run as well.

         What I modified is hello world demo ,the code would  run after DDR init ,the code what I have changed as following :

void main ()
{
    char                    version_msg[] = "\r\n\r\nPCIE Boot Hello World Example Version ";
    char                    boot_msg[80];
    platform_info           pform_info;
    uint32_t                core;
	platform_init_flags     init_flags;
    platform_init_config    init_config;
    volatile uint32_t* lvMarPtr;
    unsigned int L_Value, H_Value;
    lvMarPtr = (volatile uint32_t*)0x08000020;
    H_Value = 0x90000017;
    //platform_init(&init_flags, &init_config);

	if (DNUM == 0)
    {


		/* Initialize UART */

		platform_uart_init();
	    platform_uart_set_baudrate(BOOT_UART_BAUDRATE);


        //printf("%s%s\n\n", version_msg, version);

        write_uart(version_msg);
        write_uart(version);

        write_uart("\r\n\r\nBooting Hello World image on Core 0 from PCIE ...");

        platform_get_info(&pform_info);

        /* Unlock the chip registers */
        DEVICE_REG32_W(KICK0, 0x83e70b13);
        DEVICE_REG32_W(KICK1, 0x95a4f1e0);
        L_Value = 0x8110003f    ;
        *lvMarPtr++ = L_Value;
        *lvMarPtr++ = H_Value;
        /* Writing the entry address to other cores */

        for (core = 1; core < pform_info.cpu.core_count; core++)
        {
            sprintf(boot_msg, "\r\n\r\nBooting Hello World image on Core %d from Core 0 ...", core);
            write_uart(boot_msg);

			DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)&_c_int00);

			/* Delay 1us sec*/
            platform_delay(1);
        }
        for (core = 1; core < pform_info.cpu.core_count; core++)
        {
            /* IPC interrupt other cores*/
            DEVICE_REG32_W(IPCGR(core), 1);
            platform_delay(1000);
        }
        DEVICE_REG32_W(BOOT_MAGIC_ADDR(0), 0);
        start_boot(0);
        printf("%s\n",version);
    }

	else
		{
		/* Initialize main Platform lib */

		//printf("simon11111111");
		//sprintf(boot_msg, "\r\n\r\n core %d start...", DNUM);

		 if (DNUM == 1) L_Value = 0x8120003f    ;
		 if (DNUM == 2) L_Value = 0x8130003f    ;
		 if (DNUM == 3) L_Value = 0x8140003f    ;
		 if (DNUM == 4) L_Value = 0x8150003f    ;
		 if (DNUM == 5) L_Value = 0x8160003f    ;
		 if (DNUM == 6) L_Value = 0x8170003f    ;
		 if (DNUM == 7) L_Value = 0x8180003f    ;

	     *lvMarPtr++ = L_Value;
	     *lvMarPtr++ = H_Value;

		DEVICE_REG32_W(BOOT_MAGIC_ADDR(DNUM), 0);
		start_boot(DNUM);

		//write_boot_magic_number();
		//platform_delay(1000);
		}


}

      you can see I have added the code about  configure MPAX register ,and about the function of start_boot(),as following :

void
start_boot
(
	uint32_t n
)
{
    void                (*exit)();
    uint32_t            entry_addr;

    while(1)
    {

        entry_addr = DEVICE_REG32_R(BOOT_MAGIC_ADDR(n));
        if (entry_addr != 0)
        {
            /* jump to the exit point, which will be the entry point for the full IBL */
            exit = (void (*)())entry_addr;
            (*exit)();
        }
        platform_delay(1);
    }
}

  So according to the above code ,every core would  configure MPAX register,after complete ,it will clear their own magic address and wait for new entry address to be written .core 0 would write the entry address to core 1.....7 ,and linux pc would write the entry address to core 0. the entry address is about my test code .According to the above picture I replied Raja,the entry address is 0x90006EAC,and  core 0....6 can run as well,core 7 can't .

   Thank you .

   Simon