UMAP?

Hi Jerry

Seems like some of the design specification jargon seeped into the software/documentation. The simplest way to define UMAP0/1 is that these are design name for port0/1 for the L2 memory controller.

In the datasheet it mentions

The L2 memory configuration for the TCI6482 device is as follows:
· Port 0 configuration:
– Memory size is 2096KB
– Starting address is 0080 0000h
– 2-cycle latency
– 128- נ 4 bit bank configuration
· Port 1 configuration:
– Memory size is 32K bytes (this corresponds to the internal ROM)
– Starting address is 0010 0000h
– 1-cycle latency
– 256- נ 1 bit bank configuration

Regards

Mukul

I'm still wondering how TI is able to squeeze 2096 KiB into an byte-addressable space between 0x0080 0000 and 0x009F FFFF (... == 2048 KiB) ....

Jerry

I am not sure if I completely understand the query.

0x9FFFFF – 0x800000 = 1FFFFF = 2097151 addresses. I agree that I think the technically correct notation should be 1K = 1024 bytes and therefore ~ 2048K instead of 2096K ( I have seen folks use 1K =1000 bytes also). Either ways you should be able to get 2096K addresses , agreed?

Let me know if I am missing something.

Regards

Mukul

Ok, in this case we let DDR2 space not be 512 MB, but ~ 536.87 MB

I have submitted a documentation ticket on the datasheet to change it from 2096K to 2048K.

Regards

Mukul